TPS5432: Output is a Sine Wave

Hi,

I will review the details and provide a feedback later today.

Regards,

Febin

Hi,

Firstly, I would like to confirm a few things.

- TPS5432 is a very old part. Why does the customer use this part?

- Or was the device in their application for a very long time, and they saw the problem only now? 

- If it was a design reuse, has something else changed on their board compared to the old version?

- What is the End-equipment?

Regards,

Febin

Hello Febin,

Good day.

Hi,

Thanks for sharing the details.

I strongly recommend to choose one of our newer bucks which not only has a better performance & cost benefit but will also be much better in terms of availability in future. Please have a look at our TPS6282xA family, TLV62568A/569A, TLV62585 or our latest cost optimized solution TPS62A01A (currently only 1A RTM, 2A sampling). If you need a COMP pin then TPS62850x would be another option.

TI-CSC said:

The circuit we used in our design was taken from TI's Webench circuit simulator.

The default compensation components generated in Webench for your Vin, Vout, Iout conditions is different from what is being used in your design.

Is there any reason for changing the compensation? If so, can you share the details of the design?

I think during the transient load, the device is not able to stabilize the output with this compensation. Can you try the default design in your application and check if the Vout is stable?

Regards,

Febin

Hello Febin,

Good day.

We suspected the compensation network at the beginning of this issue, so we have changed the resistor and capacitor values as per Webench design values, but the same issues are repeating again. We have tried every possible way as per our knowledge. This was a mass order of 10k units and implemented it too, so we have to resolve this issue. On the TI website, we have found this part is still active(no EOL details found), that's the reason we are using it in our project, please recreate this scenario and give a solution for this issue.

Thank you and let me know if you need further information.

Regards,

CSC

Hi,

TPS5432 is not EOL. But we have much better devices in our portfolio and would like to recommend the new devices for newer projects.

Please share the waveforms for Vin, Vout, I_L, PH during the load transition.

Please share the complete schematic used for these measurements.

Could you share the layout?

Do you also have the TPS5432 EVM? If so, please perform the same tests on the EVM first. Unfortunately, I do not have these old parts in our local inventory.

Regards,

Febin

Hello Febin,

Good day.

Hi CSC,

Thank you for all the scope plots and layout.

I have a strong feeling it is a stability issue. It is usually triggered by an event like load transient (as in your case).

Have you also tried Bode plot simulations with your design to understand loop stability?

I will try some simulations this week and update you...

Regards,

Febin

Hello Febin,

Hi,

I will update you by Friday.

Regards,

Febin

Hi CSC,

Thanks a lot for your patience and understanding...

- Are all the PCB having just two layers?

- The schematic seems to be different for all TPS5432 regulators. 1.2 & 1.8V regulator seems to have high inductance. I am not sure why you need such high inductor values.

- Are all three units on the same board? If on the same board, is the load test for all three conducted simultaneously or individually? 

- I simulated Bode Plot in PSPICE with the above Schematic for 1V regulator and looks like the BOM is stable. However the parasitics on a real board will be different from the ideal environment in simulations.

So, what I suggest is to perform Bode plot measurements on the customer board. From what I understood, when you apply constant load at start-up, then there was no issue. Therefore; please provide 100mA and 1A constant load at start-up to avoid the problematic output. You can then check the transient load case.

- The sine wave frequency of 35kHz that you observe may not be the right measurement. Because this device has OVTP feature and the output voltage overshoot will be controlled. Which means the period of the sine wave could get longer without such a feature. So, it is important to understand if the system is stable with the customer BOM.

- The full schematic of the board was not attached. What is the pre-regulator & actual load for each regulator? Also, it's not clear for me if there are more output capacitors on the customer board close to the load? 

- 

TI-CSC said:

(we have isolated the other section during the load test)

Do you mean during the load test, only rheostat is connected at the load of the TPS5432 and no other rails on the output of TPS5432. Is the problem occurring only during the load test or even during normal operation?

- Is the 3.3V supply on the same board as TPS5432 during the load test?

- How many boards have been tested so far?

- Can you also probe COMP pin for the following conditions:

  Case 1- constant 1A load at start-up

  Case 2- constant 100mA load at start-up

  Case 3- Load transient from 100mA to 1A

- Layout Review to follow.

Please let me know if it is necessary to have a call to discuss further.

Regards,

Febin

Hi CSC,

Layout Review:

1V Regulator-

Overall the schematic looks good. However, I am not quite sure of the grounding of the f/b divider, COMP & SS pins... 

Is there any connection to GND planes underneath or to the thermal GND or analog GND?

"The sensitive analog ground connections for the feedback voltage divider, compensation components and slow start capacitor should be connected to a separate analog ground trace." As per the datasheet example, they should share a connection to the POWER GND, THERMAL PAD or ANALOG GND.

1.2V Regulator-

- There is an additional ferrite bead at the output. If not properly designed, this could contribute to stability issues.

- Where do you measure Vout? Before or After Ferrite Bead?

- Grounding of the f/b divider, COMP & SS pins (same as 1V regulator)

- How long is the trace from Vout to F/b loop? How many layers does the PCB have?

- What are these components under U15?

1.8V Regulator-

- There is an additional ferrite bead at the output. If not properly designed, this could contribute to stability issues.

- Where do you measure Vout? Before or After Ferrite Bead?

- Grounding of the f/b divider, COMP & SS pins (same as 1V regulator)

- How long is the trace from Vout to F/b loop? How many layers does the PCB have?

- What are these components under U16?

Further Questions:

- Are all three units on the same board?

- If on the same board, is the load test for all three conducted simultaneously or individually?

- If on the same board, when you make changes to the BOM, are all three regulators modified and re-tested simultaneously? 

I suggest to evaluate one regulator at a time and isolate all others. Make necessary changes to the BOM and individually perform Bode Plot measurements. Please remove the FB if possible.

Regards,

Febin

Hello Febin,

Below are the responses.

The schematic seems to be different for all TPS5432 regulators. 1.2 & 1.8V regulator seems to have high inductance. We are not sure why you need such high inductor values.

>> The schematics we sent to you was a reference that we initially used in the board.

After we found this problem, we reduced the inductor value, changed the compensation network, increased the capacitor value too, we have done so many changes in our board to resolve this issue, that's why I'm not able to send all the schematics change's I have made. So we conclude that even though we change the inductor value it's repeating the same.

We simulated Bode Plot in PSPICE with the above Schematic for the 1V regulator and looks like the BOM is stable. However, the parasitics on a real board will be different from the ideal environment in simulations.

>> Did you check this issue on your board ? Kindly check with the practical board in scenario's which I have explained so you can get this issue.

What we suggest is to perform Bode plot measurements on your board. From what I understood, when you apply constant load at start-up, then there was no issue. Therefore; please provide 100mA and 1A constant load at start-up to avoid the problematic output. You can then check the transient load case.

>> Yes it looks fine, but we have used 3 regulators in each board and we are going to manufacture 10k board's, so 30k regulators we are going to use. We are using this regulator for ethernet PoE so many board's will be connected across it and in the end application there will be lots of switching inside the board will happen , this may lead to any functionality issues in future. So we are requesting you a solution to avoid problem's the future.

The sine wave frequency of 35kHz that you observe may not be the right measurement. Because this device has OVTP feature and the output voltage overshoot will be controlled. This means the period of the sine wave could get longer without such a feature. So, it is important to understand if the system is stable with your BOM.

The full schematic of the board was not attached. What is the pre-regulator & actual load for each regulator? Also, it's not clear to us if there are more output capacitors on your board close to the load? 

Do you mean during the load test, and only rheostat is connected at the load of the TPS5432 and no other rails on the output of TPS5432. Is the problem occurring only during the load test or even during normal operation?

>> During load test, only rheostat alone is connected, no other rails are joined. During load test three regulator's give the same response; it generates an output as sine wave kind with their respective voltage offset. But in the practical case only 1V regulator produces these sine waves with the same frequency but with less peak to peak voltage, these are all clearly mentioned in scope diagrams. In the diagram below, it was 1V output scope for your reference. We cannot consider this as a ripple because it has different frequency values and less peak to peak amplitude, but when under load test it behave's same as other regulator's.

- Is the 3.3V supply on the same board as TPS5432 during the load test?

>>Yes it is on the same board, we have tested input voltage at the time of load transient , it was stable and no changes occurred during this issue.

- How many boards have been tested so far?

>> We have tested 2 boards so far totalling 6 regulator's.

- Can you also probe COMP pin for the following conditions:

  Case 1- constant 1A load at start-up

  Case 2- constant 100mA load at start-up

  Case 3- Load transient from 100mA to 1A

>> Ok we will check on it .

- Layout Review to follow.

Below are additional questions:

Are all the PCB having just two layers?

>> No, it was an 8 layer board, but the regulator section was only in the top and bottom layer, So no other layers are included.

Are all three units on the same board? If on the same board, is the load test for all three conducted simultaneously or individually? 

>> Yes , all three are on the same board. We did load tests individually for each regulator.

On PCB Layout:

1V Regulator-

Overall the schematic looks good. However, we are not quite sure of the grounding of the f/b divider, COMP & SS pins.

Is there any connection to GND planes underneath or to the thermal GND or analog GND?

>> Yes, there is a Ground layer next to Top layer, and before the bottom layer too.

"The sensitive analog ground connections for the feedback voltage divider, compensation components and slow start capacitor should be connected to a separate analog ground trace." As per the datasheet example, they should share a connection to the POWER GND, THERMAL PAD or ANALOG GND.

>> We have used a lot of TI DC/DC part's using this layout style, they also have COMP network, FB voltage driver, SS capacitor's and they are connected to the same ground and no issues are observed. Only in this TPS5432 part we are observing these change's. They are sharing connections with Power Gnd, Thermal Pad or AG . Unfortunately we do not have enough time to change and validate, already boards are builded.

>> Please work on EVK of TPS5432 to observe this result ,so that you can get exact outcomes.

1.2V Regulator-

- There is an additional ferrite bead at the output. If not properly designed, this could contribute to stability issues.

- Where do you measure Vout? Before or After Ferrite Bead?

>> As per our design , there is no issue due to the ferrite bead, because the load is connected after removal of the ferrite bead. Vout is measure before ferrite bead.

- Grounding of the f/b divider, COMP & SS pins (same as 1V regulator)

>> Same layout as 1V regulator.

- How long is the trace from Vout to F/b loop? How many layers does the PCB have?

>> we designed as minimum as possible to connect Vout to the feed back pin.

- What are these components under U15?

>>These are the components that drives the enable pin of the Regulator. We probed these signals too and looks fine.

1.8V Regulator-

- There is an additional ferrite bead at the output. If not properly designed, this could contribute to stability issues.

- Where do you measure Vout? Before or After Ferrite Bead?

- Grounding of the f/b divider, COMP & SS pins (same as 1V regulator)

- How long is the trace from Vout to F/b loop? How many layers does the PCB have?

- What are these components under U16?

>> Answers same as the above 1.2V regulator.

We suggest evaluating one regulator at a time and isolating all others. Make necessary changes to the BOM and individually perform Bode Plot measurements. Please remove the FB if possible.

I will wait for your response regarding these observations.

>> We removed all the ferrite beads and evaluation is done one regulator at a time.

Thank you for your support.

Regards,

CSC

Hi CSC,

Thank you for all the information.

I can check the loop stability on a standard EVM and try to vary the load using a rheostat. I will be using recommended BOM based on the datasheet and not the customer BOM. But I think it will be hard to replicate the issue on an EVM because I still do not have clarity on the full schematic and layout of the customer. 

I will order the EVMs today and hopefully I will get it next week and start measurements then. I will update you by end of next week.

Open questions:

Febin said:

- The full schematic of the board was not attached. What is the pre-regulator & actual load for each regulator? Also, it's not clear for me if there are more output capacitors on the customer board close to the load? 

- What is the pre-regulator device and load device for each regulator?

- Are there additional Cout close to the load?

- Waiting for COMP pin measurements.

- Waiting for loop stability measurements for each regulator in normal operation on customer board. Please remove the FB & isolate from other circuits at the output.

Regards,

Febin

Hello Febin,

This is the response from the customer:

We are waiting for a response from your side. I remember that you will check on TPS5432 EVM and update us on the results.

Meanwhile, I have probed the COMP pin and it’s look’s fine even though the issue created on the output side.

So, I conclude that there is no problem with the COMP network. (we have already reworked the board with a suitable resistor and capacitor suggested by TI webench, but still, this issue occurs).

 I’m not allowed to share the full schematics for other organizations, but I have made a request to my manager about sharing the partial schematics with you. The pre-regulator will have a 3.3V regulator and the post-regulator will have a high-end processor. But we did all the tests by isolating the load on board. We have already shared the input side waveforms with you and there is no issue on the input side.

 We only mounted two 22uF capacitors on the output side.

 We did all these measurements by isolating FB (Ferrite Bead) from the rest of the circuits. The output side of the regulator is only connected to the rheostat.

 We have tried many possibilities to solve this issue, kindly work with your side and update us.

Please do it in your EVM and kindly try to recreate this issue in the scenarios I have mentioned in my previous emails.

Thank you in advance for your support.

Regards,

CSC

Hi CSC,

I received the EVMs yesterday. I need some time to perform the measurements. I hope to update you latest by early next week.

Regards,

Febin

Hi CSC,

Firstly, let me thank you for your patience and understanding.

I tried to recreate the customer test scenario using a standard TPS5432 EVM.

1. Constant load of 100mA at start-up

2. Constant load of 1A at start-up

3. Constant load of 100mA at start-up and then increasing to 1A load during operation. 

In all these cases, the output voltage was stable and there was no abnormal behavior. Attached the scope plots hereby.

 4087.TPS5432EVM Measurements.zip

Do they observe this behavior while using PoE power or DC power?

Is there any other circuit that will be operational when the TPS5432 is being tested?

What is the intention of this test? For eg, applying 100mA and then suddenly applying 850mA load in parallel?

It is very challenging to suggest solutions without having clear understanding of the customer board. What the customer can do is to completely isolate the TPS5432 from other circuits and perform Bode plot measurements. I have a strong feeling there is still some interference from other circuits on the board. Please also monitor the load current or inductor current. 

In the past we had also seen problems when the BOOT capacitor was mounted far away from the PH and BOOT pins just like this case. Can the customer try to solder this capacitor on the same layer as the IC and check if it improves. It will also be interesting to understand what is on each layer under or close to TPS5432. Hence please push the customer to share detailed schematic and layout. We can of course take this internal and discuss further.

Regards,

Febin

Hello Febin,

We have rechecked our board, the regulator was completely isolated from other circuits.
I’m unable to view the scope waveforms that you have shared with me.

 Please clarify for me, If you provided the load gradually or suddenly?

Kindly provide the sudden 1A Load and check instead of gradual raising. Because we won’t get any kind of issue while increasing the load gradually.

Our board supports 54V passive POE, the 54V is stepped down to 3.3V. This 3.3V supply is the source for all other regulators. We probed that voltage too, but there are no changes observed at the time of this issue.  

 We are planning for 10K production PoE boards per year. To avoid problems in the future, now we are trying to solve this issue.

 We have released the design due to time constraints, so now we are allowed only for minor changes.

 I will try my level best to share the schematics with you. I will talk with my superior for sharing schematics with you.

Thank you in advance.

Regards,

CSC

Hi CSC,

Reattached the scope plots.

1460.TPS5432EVM Measurements.zip

TI-CSC said:

 Please clarify for me, If you provided the load gradually or suddenly?

I gave a sudden increase. However, please consider the transition time required for a rheostat from 100mA to 1A.

Febin said:

- Waiting for loop stability measurements for each regulator in normal operation on customer board. Please remove the FB & isolate from other circuits at the output.

Any updates on Bode plot measurements from the customer side?

Febin said:

In the past we had also seen problems when the BOOT capacitor was mounted far away from the PH and BOOT pins just like this case. Can the customer try to solder this capacitor on the same layer as the IC and check if it improves.

Can they try this on just one board by manual soldering?

What is the inductor part number? Did they check inductor current during this transition?

Is it possible to check the same on an EVM from your setup? This will help understand if there is something wrong with your set-up.

Regards,

Febin

Hello Febin,

A good day to you. (bold characters are from our side)

Please clarify for me, If you provided the load gradually or suddenly.

>> We have provided the load suddenly. TPS5432 actually shows random behavior, sometimes the output becomes unstable when we suddenly connected the high load to it, and sometimes when we disconnected the high load from TPS5432, it gives the same response. TPS5432 becomes unstable in either one of the above conditions.

 Actually, we did our validation by removing FB(Ferrite Bead) and isolating the entire circuits from the regulator output. TPS5432 is only connected to the rheostat alone.

 Any updates on Bode plot measurements from your side?

>> We did a Bode simulation on TI Webench and its looks fine. I think from our side you have already done this simulation.

 What is the inductor part number? Did you check the inductor current during this transition?

>> NRS5024T6R8MMGJ, NRS5024T100MMGJ, NRS5024T3R3NMGJ

>> The output signal from the PH pin itself varies during this issue. All the inductor and PH pin measurements I have shared already.

 Can they try this on just one board by manual soldering? (regarding boot capacitor)

>> We reworked and checked the condition again the issues are repeating.

>> We will check with schematics and layout for TPS5432 EVM on the TI website. Hoping it has on your website.

>>Additionally:

If you have any manual for loop stability measurement, kindly share it with me.

Kindly check with our layout and schematics, and update us if there is any issue.

1715.Design files (2).zip

Thank you so much for your continuous support.

Regards,

CSC

Hi CSC,

Please find below the Application Note from OMICRON. I use Bode100 to perform loop stability measurements.

https://www.omicron-lab.com/fileadmin/assets/Bode_100/ApplicationNotes/DC_DC_Stability/App_Note_DC_DC_Stability_V3_3.pdf

Please perform loop stability measurements on the customer application board with the problematic test conditions.

I will review the design files and come back to you today/tomorrow.

Regards,

Febin

Hi CSC,

I reviewed the schematic and it looks good...

I tried to open the .brd file using Allegro Physical Viewer. Unfortunately, the layer with the component naming was not included and it is difficult to locate U15, U16, U17.

Regards,

Febin

Hi CSC,

Do you need any further support?

Regards,

Febin