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TLV752: maximum output capacitance concerns

Cosmin P
Intellectual 1650 points
Part Number: TLV752

Hello Team,

Customer considers using the TLV752 with higher output capacitance than the datasheet recommends.
Target output capacitance is 1500uF, ceramic capacitors.

From the datasheet we can assume that the output SS will be governed by the two current limits (if temperature does not trigger the thermal protection) and that the output capacitance discharge when Vin collapses can be an issue.

- Bar using a Vin-Vout schottky, if the EN is tied to Vin, would this keep the internal FET ON and minimize the thermal shock?
- Is the high capacitance / low ESR a stability concern?
- what is driving the Coutmax limitation otherwise?

Thank you

  • 0
    TI__Mastermind 48825 points

    Hi Cosmin,

    Cosmin P said:
    - Bar using a Vin-Vout schottky, if the EN is tied to Vin, would this keep the internal FET ON and minimize the thermal shock?

    Do you mean when the input collapses?

    Cosmin P said:
    - Is the high capacitance / low ESR a stability concern?

    It is possible this could be a concern for stability. I will have to consult the designers to evaluate the risk.

    Cosmin P said:
    - what is driving the Coutmax limitation otherwise?

    There could be a few reasons for this, and this is another point I will have to go to the designers for.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Intellectual 1650 points

    Hi Nick,

    For the first question...
    yes, at system power down I expect Vin rail to collapse faster than Vout, so the internal FET's diode will allow for reverse current flow hence heating up the LDO.
    These applications with relatively low current but huge rail capacitance are ASIC noise requirement driven, so we end up with extreme corner cases, beyond the 'usual' application target of a small LDO and its datasheet detail available.

  • 0 in reply to Cosmin P
    TI__Mastermind 48825 points

    Hi Cosmin,

    With output capacitors as large as 1500uF, there is a high chance that the part will be damaged if a reverse voltage condition happens because the peak current can be large. To be clear, keeping the pass FET on will not result in current going back through to the input - when the condition VOUT > VIN + 0.3V is present, the body diode turns on and current flows through the body diode and not back to the input. Since this device does not have integrated reverse current protection, a Schottky would be necessary to protect the device.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Intellectual 1650 points

    Hi Nick,

    -  I am not sure I understand:
       If the FET is ON, it is conducting current both ways, so current should go back to the input if Vin < Vout through the Rdson resistance
       If the intrinsic diode turns ON when Vout>Vin+0.3V then the intrinsic diode turns ON at 0.3V?
       usually a discrete FET's diode turns ON around 1V as far as I know
       Is there a separate schottky structure on the die ? 

    -   Assuming the external schottky is present, is the LDO stable with 1500uF?

    Thank you

  • +1 in reply to Cosmin P
    TI__Mastermind 48825 points

    Hi Cosmin,

    The FET (PMOS for this device) has its body tied to its source, shown in the functional block diagram:

    When a 4-terminal transistor is connected in this way it does not behave as a simple resistor. When its drain becomes larger than its source current will not conduct through the channel, it will conduct through its body. 

    The diode will likely have a forward voltage of 0.7V - 1V. Most datasheets specify the abs max for VOUT is VIN + 0.3V. Under this condition the body diode will not turn on, but going beyond VIN + 0.3V can turn it on.

    I have not heard back from the designers. This is a request that is not exactly trivial to answer and will require simulations to be sure. I will update you when I have information to share.


    Regards,

    Nick