This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS6594-Q1: TPS65941515RWERQ1:OFF sequence

Part Number: TPS6594-Q1
Other Parts Discussed in Thread: DRA821

Hi,


The GPIO of the PMIC is set to Output and used as the ENBALE input of the power supply IC.
TI' s "SLVUCD4.pdf" is used as a reference.
I have confirmed that both rise and fall are controlled as I designed.
However, we confirmed that BUCKx/LDOx/GPIOx unintentionally started up again about 50ms after the power was turned off.
Are there any countermeasures against this phenomenon? Or is it possible to avoid it with PMIC settings?

best regards,

  • Before the PMIC_ENABLE is pulled low, is the ENABLE_INT cleared?

    The GPIO of the PMIC is set to Output and used as the ENBALE input of the power supply IC.

    Which power supply IC is GPIOx connected to?

  • Dear Michael

    Thank you for responding.
    >Before the PMIC_ENABLE is pulled low, is the ENABLE_INT cleared?
    →The our prototype is not cleard "ENABLE_INT".
     I tried clearing "ENABLE_INT" once, but I didn't see any change in the waveform.
     It is possible to change ”ENABLE_MASK” from ”Interrupt gernerated” to ”Interrupt not gernerated” in GUI3, but is it possible to improve it?

    >Which power supply IC is GPIOx connected to?
    GPIO uses the following settings as Output.
    GPIO4⇒VDD_WK
    GPIO5⇒VDD1_LPDDR4_1V8
    GPIO6⇒VDD_IO_3V3

    best regards,

  • Hello, 

    I have tried to replicate what you are seeing with a TPS65941515 device, but have been unsuccessful. I do not see the CPU and CORE rails power back up. 

    1. How are you powering down your board/prototype? Do you set PMIC_EN low first or disable 3V3_VSYS supply?

    2. Does nRSTOUT turn back on after 50ms as well? If not, then the processor won't attempt to power back up, that would be a good thing.

  • Dear Michael

    Thank you for responding.

    Sorry, I didn't send the image, so I will send it.
    As a tendency, it seems that the startup after the power is turned off follows the sequence that I designed.

    >1. How are you powering down your board/prototype? Do you set PMIC_EN low first or disable 3V3_VSYS supply?
    →I plan to turn off the "3V3_VSYS (Power supply for PMIC)" after PMIC_EN is pulled low, but in the prototype, the "power supply source for 3V3_VSYS"  is turned off and PMIC_EN goes low at about the same time.
    I plan to turn off the "3V3_VSYS (Power supply for PMIC)" after PMIC_EN is pulled low, but in the prototype, the "power supply source for 3V3_VSYS" is turned off and PMIC_EN goes low at about the same time.
    However, 3V3_VSYS has a capacitor etc., so it will take some time to complete the discharge.

    >2. Does nRSTOUT turn back on after 50ms as well? If not, then the processor won't attempt to power back up, that would be a good thing.
    →As far as I can see from the waveform, the rise time is only about 10ms, and nRSTOUT is designed to rise about 20ms after the sequence starts.
    Therefore, it is expected that the power will come up but the DRA821 will not boot.

    best regards,

  • It is good the nRSTOUT does not come back up. This confirms that the DRA821 will not attempt another boot. 

    Have you edited the PFSM from what is default for the TPS65941515? After a power down sequence caused by PMIC_ENABLE going low, the PMIC should be in a standby state waiting to be awoken. If you just pull PMIC_ENABLE low and don't do anything else, do you still see this behavior?

  • Dear Michael

    Thank you for responding.
    I also measured the same points on the TPS65941212EVM.
    The same trend was seen with EVM, but does this phenomenon occur when VCCA is turned off?

    The waveform is measured at the following locations of TPS65941212EVM.
    -ch1:J45(2)/nPWRON
    -ch2: J11(4)/GPIO4

    >If you just pull PMIC_ENABLE low and don't do anything else, do you still see this behavior?
    →Even if PMIC_ENABLE is set to low, the PMIC VCCA is normally supplied, so it will not start up.

    best regards,

  • What NVM did you have programmed to the TPS65941212EVM? For the TPS65941515 and TPS65941212, GPIO4 is an input and thus the PMIC would not be controlling it. 

  • Dear Michael

    Thank you for responding.
    I'm sorry.
    In the TPS65941212EVM, GPIO4 and GPIO6 settings are changed to output according to the prototype circuit.
    Also, BUCKx (phase config) is set to “2+2+1”(Resistors have been modified accordingly).

    I removed R53 and R77 of EVM because there was a possibility that the power was supplied from MCUVCC because the resistance was not removed in the circuit diagram of EVM for the measurement data of the function.
    In the prototype circuit, 3V3_VSYS power continues to be supplied for about 50msec even after the PMIC is turned off.Is this likely to cause the PMIC to malfunction?
    (Is it better to stop the VCCA supply immediately when the power is turned off?)

    best regards,

  • Hi,

    Michael is out of office today due to US holiday. They will be back next week to look over your inquiries.

    Best,

    David

  • I removed R53 and R77 of EVM because there was a possibility that the power was supplied from MCUVCC because the resistance was not removed in the circuit diagram of EVM for the measurement data of the function.

    I believe R53 and R77 are the root cause of what you were seeing on GPIO4. The U8 and U9 on the EVM are bi-directional level shifters and MCUVCC  is pulling one side up.

    Please note that the best place to measure GPIO6 on the '1212 EVM is on J29, but with R69 removed.

       

    In the prototype circuit, 3V3_VSYS power continues to be supplied for about 50msec even after the PMIC is turned off.Is this likely to cause the PMIC to malfunction?

    This should not cause the PMIC to malfunction. The PMIC should have completed it's power down sequence well before then.