Other Parts Discussed in Thread: DRV8323, BQ76200
Hi everyone!
I am currently developing a new product and currently lack the ideas to solve a specific problem.
For a battery powered application with a brushless motor, I am using the following setup:
- 7 Lithium Cells in Series as power supply, this gives a 17.5V to 29.4V supply voltage range with a nominal voltage of ~25.9V
- TI BQ76930 AFE for the BMS
- TI DRV8323RS as smart gate driver paired with 6 N-FETs for the motor control
- Internal Buck DCDC converter of the DRV8323RS as power supply to the MCU
- STM32F4 (I hope I still get support from you J ) as a main MCU connected via I2C to BQ76930 and via SPI and GPIOs to the DRV8323
- Everything is tightly mounted on a single PCB to save space
My functional requirements are:
- STM32 is supplied by the 3V3 DCDC in the DRV, which will be enabled by an external switch => DRV needs to be connected to Battery Power continuously.
- BMS needs to be able to disable current in/out of the battery in case of fault conditions for the charger and for the motor power stage. The BQ76930 allows to do this via its outputs for the charge and discharge fets. It is enough, to disable power to the power stage of the motor and keep the rest of the system (sensors, MCU, etc.) connected.
- It is preferred to use only low-side N-FETs for this task to save cost and get rid of any gate driving (power consumption in idle state)
- BMS (BQ76930) GateDriver (DRV8232RS) and MCU (STM32F4) should have the same ground to not need any isolation in between.
The main question is where to place the Charge and Discharge N-FETs in the schematic. Initially, the structure was as follows: Negative of Cell 0 => BMS Shunt => CHG/DCHG FETs => System GND. This Setup, however, destroys the BQ IC, as soon as you turn off the FETs, as all communication lines pull to U_BAT. Also, the system is then in a dead state: You cannot turn on the MCU anymore, because the DCDC is also disconnected. But you also cannot reset the BMS, because the MCU is dead.
An updated solution inserts the charge and discharge N-FETs between an “intermediate GND” for all motor half-bridges and the system GND. This supplies the Buck DCDC of the DRV at all times and also offers a common ground for the MCU and BMS so no isolation is necessary. See attached schematic for a better understanding.
The possible problem I see with this solution is: When we turn off the GND for the Power Stage but have Logic GND still connected, the input pins from the current sense resistors (SLx and SHx) pull to U_Bat (because everything is floating at U_BAT). This greatly exceeds the absolute maximum ratings of SLx of 1V.
Any ideas on how an ideal solution to this problem might look like?
Your help is highly appreciated!
Thanks,
Jakob
