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Original question:

66AK2G12: About ASRC data input/output

66AK2G12: About ASRC data input/output(Again)

O.H
Mastermind 6350 points
Part Number: 66AK2G12

Hi experts,

The original thread was locked with no updates, so I'll repost it.

Please tell me about the ASRC built into the 66AK2G12.

Q1:Is it correct that the data input/output to ASRC must go through TeraNet_DMA? Or, is it possible to input data directly from McASP to ASRC, process it, and then output it again via ASRC in McASP?

Q2:For example, is it possible to take a signal at 96.1kHz from McASP, process it at 96kHz internally via ASRC, and then output it at 96.1kHz via ASRC again?

Q3:According to "11.1.3.3 ASRC Data Interface and Formats" in TRM, is it correct to truncate the MSB of a 32-bit input from McASP for a maximum 24-bit input/output? Or is it LSB truncation?

Our customer is starting to design a motherboard (audio I/O, etc. except K2G and C6657) for evaluation. So, I would like to know if I need a separate external ASRC or not, and I would appreciate your help.

If you have difficulty answering the part about ASRC, or if you can answer offline, please let us know which one.

Best regards,
O.H

  • 0
    TI__Mastermind 30140 points

    Hi O.H,

    O.H said:
    Q1:Is it correct that the data input/output to ASRC must go through TeraNet_DMA? Or, is it possible to input data directly from McASP to ASRC, process it, and then output it again via ASRC in McASP?

    It is not 100% clear. The data must go through TeraNet_DMA and since ASRC is a slave, the data transfer must be initiated by a master. McASP is not a master either, so some other master would have to move data from McASP to ASRC. It seems to have been intended for EDMA to move data from McASP to ASRC, but TRM 11.1.3.1 ASRC Block Diagram and Implementation reads... "As an alternative to EDMA moderated data input and output ASRC data transfers, the ASRC also supports input FIFO and output FIFO interrupts to permit a device processor to control the data transfers" And there does appear to be a path between MSMC and ASRC in TRM Figure 3-2. TeraNet_DMA Master-Slave Connections Based on that it seems the CPU could move the data instead of the EDMA, however TRM Table 3-3. TeraNet_DMA Connectivity Matrix has an 'N' between C66X_COREPAC_0_CFG and ASRC. N – There is no connection between this master and the bridge. For these reasons, I will reach out for help internally and hope to get back to you next week.

    O.H said:
    Q2:For example, is it possible to take a signal at 96.1kHz from McASP, process it at 96kHz internally via ASRC, and then output it at 96.1kHz via ASRC again?

    Yes, I believe so. The path would be something like 1) Read register from McASP to ASRC FIFO (or maybe into memory) 2) Service interrupt from ASRC and read sample(s) from FIFO to memory (96kHz sampling) rate 3) Process audio internally and write to ASRC FIFO (or maybe into memory) 4) Sercice interrupt from ASRC and read sample(s) from FIFO to McASP memory mapped register It would be more efficient to copy blocks of data at a time instead of sample by sample DMA is well suited to copying blocks of data without interrupting CPU (except to notify that the data is copied)

    O.H said:
    Q3:According to "11.1.3.3 ASRC Data Interface and Formats" in TRM, is it correct to truncate the MSB of a 32-bit input from McASP for a maximum 24-bit input/output? Or is it LSB truncation?

    Yes. The note in TRM Section 11.1.3.3 ASRC Data Interface and Formats reads... "The only internal data format is of a 28-bit sample. Externally, the only format supported is a packed 24-bit samples into a 32-bit word, as described in this section."

    O.H said:
    Our customer is starting to design a motherboard (audio I/O, etc. except K2G and C6657) for evaluation. So, I would like to know if I need a separate external ASRC or not, and I would appreciate your help.

    The intent of the ASRC is to prevent the need for separate external ASRCs, but evaluation of the performance must be completed by the customer. Will get back to you about the CPU access to ASRC data.

    Regards,
    Mark

  • 0 in reply to Mark M
    Mastermind 6350 points

    Hi Mark, 

    Thank you for your polite answer.

    Mark M said:
    "As an alternative to EDMA moderated data input and output ASRC data transfers, the ASRC also supports input FIFO and output FIFO interrupts to permit a device processor to control the data transfers" And there does appear to be a path between MSMC and ASRC in TRM Figure 3-2. TeraNet_DMA Master-Slave Connections Based on that it seems the CPU could move the data instead of the EDMA, however TRM Table 3-3. TeraNet_DMA Connectivity Matrix has an 'N' between C66X_COREPAC_0_CFG and ASRC. N – There is no connection between this master and the bridge. For these reasons, I will reach out for help internally and hope to get back to you next week.

    I understood. We look forward to additional information.

    Mark M said:
    O.H said:
    Q3:According to "11.1.3.3 ASRC Data Interface and Formats" in TRM, is it correct to truncate the MSB of a 32-bit input from McASP for a maximum 24-bit input/output? Or is it LSB truncation?

    Yes. The note in TRM Section 11.1.3.3 ASRC Data Interface and Formats reads... "The only internal data format is of a 28-bit sample. Externally, the only format supported is a packed 24-bit samples into a 32-bit word, as described in this section."

    I apologize for the poor expression of my question. Let me check again.

    Does the idea when 32-bit data from McASP is input to ASRC match the following idea?
    McASP: 0x12345678 [31: 0]
    ASRC:   0x00345678 [23: 0]

    Best regards,
    O.H

  • +1 in reply to O.H
    TI__Mastermind 30140 points

    Hi O.H,

    Mark M said:
    Q1:

    Sorry about my TeraNet_DMA confusion. A master like ARM, C66x, or EDMA is required to initiate the data transfer from McASP to ASRC and back. Since the ASRC hangs off of the TeraNet_DMA, all data paths to/from ASRC will have to go through TeraNet_DMA. The different routes depend on which interconnect the master hangs off. Refer to below figure.



    Notice how the C66x CFG takes a different path compared with C66x XMC and ARM Core Pac.
    To explain that, refer to 6.2.1 DSP Subsystem Overview.
    • External Memory Controller (EMC):
      – Internal DMA (IDMA) engine
      – One 128-bit VBUSM slave port from TeraNet_DMA
      – One 32-bit VBUSP master port to TeraNet_CFG
    • XMC (Extended Memory Controller):
      – One 256-bit port to MSMC controller
    Compare this against Figure 11-1. ASRC Overview Diagram (color-coded below) and you'll see that the path from C66x to Configuration MMR goes through TeraNet_CFG. Whereas the path from C66x to Audio Data MMR goes through TeraNet_DMA, via MSMC with the XMC.


    In TRM, the below tables explain in a different way the difference in paths.
    Table 3-3. TeraNet_DMA Connectivity Matrix - C66X_COREPAC_0_CFG to ASRC_0_S does not take TeraNet_DMA path
    Table 3-5. TeraNet_CFG Connectivity Matrix - C66X_COREPAC_0_CFG to ASRC_0_CFG does take TeraNet_CFG path (for configuration MMR)

    What is not shown in these tables is that C66X_COREPAC_0_MDMA_MST does have a path to ASRC_0_S through TeraNet_DMA (for Audio Data MMR)

    In general, C66x has access to everything in the device. ARM also.

    O.H said:

    Q3: I apologize for the poor expression of my question. Let me check again.

    Does the idea when 32-bit data from McASP is input to ASRC match the following idea?
    McASP: 0x12345678 [31: 0]
    ASRC:   0x00345678 [23: 0]

    Refer to TRM 11.1.3.3 ASRC Data Interface and Formats

    The ASRC data format is little endian, with up to 24-bit samples of data packed into 32-bit word.
    Bits [31:24] are always '00'. A 24-bit number will reside in bits 23:0 as you have shown for all cases.
    A 16-bit number will reside in bits [23:8]  when Auto Alignment is Disabled or [15:0] when
    Auto Alignment is Enabled.

    McASP includes features to mask, pad, and rotate samples to aid in these types of conversions. Refer to TRM 11.9.4.4 McASP Format Units

    Regards,
    Mark

  • 0 in reply to Mark M
    Mastermind 6350 points

    Hi Mark,

    Sorry for the late reply. Thank you for your thoughtful response.

    We will evaluate the system in actual operation based on the information you provided and will contact you again if any problems arise.

    Best regards,
    O.H