TDA4VM: TDA4 turned on L3 cache, but the CPU load did not improve

Tongxin Wang

Part Number: TDA4VM

Hi，Expert：

Based on (+) TDA4VM: TDA4 L3 cache - Processors forum - Processors - TI E2E support forums

I configure L3 cache (6MB) for our custom board. . Here are my board config:

    /* tisci_boardcfg_msmc */
    .msmc = {
        .subhdr = {
            .magic = TISCI_BOARDCFG_MSMC_MAGIC_NUM,
            .size = (uint16_t) sizeof(struct tisci_boardcfg_msmc),
        },
        /* If the whole memory is X MB the value you write to this field is n.
         * The value of n sets the cache size as n * X/32. The value of n should
         * be given in steps of 4, which makes the size of cache to be
         * configured in steps on X/8 MB.
         */
        .msmc_cache_size = 0x18,
    },

I called Scliet_msmcQury() API to check:

msmcQuery resp.start_low 70000000,  resp.start_high 00000000 ,  resp.end_low 701effff , resp.end_high 00000000

Here are CPU load before and after：

before：(8M msmc used as sram， .msmc_cache_size = 0x0, )

after：(2M msmc used as sram， .msmc_cache_size = 0x18, )

From Scliet_msmcQury API ,It looks like the configuration was successful, but why isn't the CPU load improving? Neither Main Domain nor MCU Domain improved.

Here are some questions:

Q1: When I configured MSMC as L3 Cache, did I miss any steps ?

Q2：If both code and data are run on DDR, is it possible to configure MSMC for L3 Cache to improve operating efficiency?

Q3：Configure MSMC as L3 Cahce, is it beneficial for Main Domain or for all Domains？

over 1 year ago

0 Keerthy J over 1 year ago

TI__Guru*** 149350 points

Hi,

Do you see a difference w.r.t memory performance? Cpuload depends on how active the CPU is whether it's cache or DDR. You can save cpuload if you enable dma for memory accesses.

Best Regards,

Keerthy

0 Tongxin Wang over 1 year ago in reply to Keerthy J

Intellectual 520 points

Hi,

At the beginning of our project, all the code section and data section were running on ddr, but we found that only the basic software was running, and the cpu load was as high as 60%. Then we only changed the link file and put most of the code section and data section to run on MSMC or OCRAM, the cpu load is reduced to 30%. So we analyze that the current bottleneck exists in the speed of fetching instructions. We think that using MSMC as L3 CACHE will greatly increase the speed of fetching instructions, but this is not the case.

We don't have a good understanding of MSMC and L3 cache, can you answer these three questions?

Tongxin Wang said:
Q1: When I configured MSMC as L3 Cache, did I miss any steps ?

Q2：If both code and data are run on DDR, is it possible to configure MSMC for L3 Cache to improve operating efficiency?

Q3：Configure MSMC as L3 Cahce, is it beneficial for Main Domain or for all Domains？

+1 Keerthy J over 1 year ago in reply to Tongxin Wang

TI__Guru*** 149350 points

Tongxin Wang said:
Q1: When I configured MSMC as L3 Cache, did I miss any steps ?

The code change that you have done is Right to configure MSMC with 6MB as L3 Cache.

Tongxin Wang said:
Configure MSMC as L3 Cahce, is it beneficial for Main Domain or for all Domains？

It is beneficial for A72 as the L3 cache is used for A72 speed up.

Tongxin Wang said:
Q2：If both code and data are run on DDR, is it possible to configure MSMC for L3 Cache to improve operating efficiency?

L3 cache in general should help improving access latencies from DDR to A72.

- Keerthy