Hello Support,
I would like to support 2 devices on the AM64x OSPI interface:
- boot flash
and
- MRAM.
Boot flash at CS0, the MRAM at CS1.
I would connect both devices completely parallel to the signals.
DQS from flash/MRAM to CPU via 22R and then a Y-distribution.
The rest of the data signals would be connected in parallel.
Flash on top, MRAM on bottom to keep the stubs as short as possible.
Question 1: Would this be possible? In principle the OSPI should be accessible for the MRAM during operation, right?
Question2: Is there a PCB routing guideline from TI, which length the DQS signal must be routed from the Flash/MRAM to the CPU? Same length as the data signals?
And what is the length to pin LBCLK0?
Regards
Daniel