Other Parts Discussed in Thread: DRA829
Dear TI Team,
I'm currently making a preliminary analysis of the DDR initialization sequence from TI SBL cause we are going to re-write it in the nearest future.
Of course there are lots of questions regarding thousand register settings but I would like to keep it currently out of the scope and ask here more common question regarding DDR initialization:
- Board_DDRPriorityInit function performs mapping of the VBUSM.C priority to DDR controllers's priority for HPT and LPT traffic, all to low prio (7).
Does it make sense to pay a lot of attention to this setting to optimize performance or the default low prio to all (7) suits most cases?
Description of these settings is very short, so if you have any additional documents, I would appreciate if you share it with me. - LPDDR4_Start function contains settings of DDRSS_PI_5.PI_INIT_LVL_EN and DDRSS_PI_5.PI_NORMAL_LVL_SEQ to 1.
I cannot link these setting to the TRM and description of the registers is unclear to me. Could you please explain these settings. - Chapter 'PI Initialization' of the TRM says that PI initialization complete is indicated by 'dfi_init_complete'. But what is 'dfi_init_complete', which register is it?
I've also noticed that somethnig like this is checked in the function LPDDR4_PollAndAckIrq, it is DDRSS_PI_79.BIT0. But description to the DDRSS_PI_79 is too vague, so I would appreciate your clarification. - DDR PLL is set in a loop with support of FSP functionality (as far as I understand), it is done in Board_DDRChangeFreqAck.
This function is somehow traceable to the TRM chapter 'DDRSS Dynamic Frequency Change Interface', but not the loop which is implemeted here.
Number of this iterations is determined by the define 'DDRSS_PLL_FHS_CNT'. In different PDK versions I saw different values - 5, 6 or 10. But I would like to understand what is the basis of these iterations, what I need to know to define this constant correctly.
And if we do not need to support two clocks and FSP, can we simplify initialization sequence here somehow? - Is DDR training a part of the current initialization routine (PDK)? If yes, where can I find the corresponding code?
- From the TRM I do not see the whole DDR initialization sequence. I can find something about controller, PI and PHY initialization, but not the complete sequence.
For example PLL is being configured after PI, PHY and controller is triggered to be initialized, but why at this time point, why not before?
Why PI and controller configuration check is done after PLL setting, but not before?
I mean the whole sequence is not very described, therefore a question: do you plan to have a new document (application note) or extend the TRM to give better overview? Currently I can hardly imagine if one can write DDR initialization routine out of the TRM only.
Best regards,
Dmitry
