TDA4VM-Q1: DDR config tool DRAM parameter unit

Hi Xingyu,

Xingyu Zhu said:

some parameters have 2 value, one of them is in ns units while the other one is in tck units

Many DRAM timing parameters are specified in both clock cycles and in ns. This comes directly from the DRAM datasheet.

The reason for having two different timing values is due to the wide frequency range supported.

As an example, a ZQ CAL LATCH command requires at least 8 cycles to complete, but also requires at least 30 ns. When a ZQ CAL LATCH command (tZQLAT) is issued at the boot frequency (<= 55 MHz), the controller should wait 8 clock cycles (~145 ns), which is much larger than 30 ns. However, when operating with a 2133 MHz clock, the controller should wait 30 ns, or ~ 64 clock cycles. 

Regards,
Kevin