TDA4AH-Q1: Reference Clock Divider - Valid values

Hi,

Scott Brown said:

In the SDK within csl_serdes3.c (line 408; CSL_serdesRefclkSel), if we want a 156.25MHz reference clock (PMA_CMN_REFCLK_DIG_DIV) the code sets the register to a value of 0x3. However in the J784s4 register spreadsheet, under the wiz16b8m4ct3 tab this is a reserved value. The only appropriate values are 0 and 2, with 3 listed as "Divide by 8 (Reserved)".

Yes, We are configuring the REFCLK_DIG_DIV to 3 when reference clock is 156.25MHz.
The same is being used in TDA4VM as well, as SerDes is same.

Scott Brown said:

Are you able to confirm the code is correct, and the register spreadsheet just hasn't been updated?

Code is correct only, might need to update the spreadsheet.

Shreyas Rao
Can you please confirm the same.

Best Regards,
Sudheer

Sudheer,

Yes, REFCLK_DIG_DIV is correct at 2b'11.