Hi Board designers, 

Refer below inputs:

1. Pullup recommendation 

The Pullup recommendations depend on the eMMC PHY implementation 

AM62x, AM62L, AM62Ax and Am62D-Q1 implement soft PHY

In soft PHY implementation, the MMC0 pins have alternate functions that can be configured.

Connect external pullup resistor for the data line (MMC0_DAT0) (close to eMMC device).
eMMC device (as long as the eMMC device is compliant to the eMMC standard) has the pullups enabled for data signals
D7..D1 by default. The eMMC device will turn off its D3..D1 pulls when entering 4-bit mode and D7..D1 pulls when entering 8-bit mode.
The eMMC host software should turn on the respective DAT pulls when it changes the mode.

AM62Px / AM64x / AM243x (ALV) implements a hard PHY

In hard PHY implementation, the MMCO pins have dedicate eMMC functionality. When not used, it is recommended to connect these pins as per the pin connectivity recommendations of the specific device data sheet.

No external pull resistors are required for MMC0 since the PHY includes and dynamically controls the internal pull resistors as required for an eMMC.
Pullups for D7..D0 and CMD are internally enabled during reset and after reset by the processor eMMC PHY.
Pulldown is enabled for the DS pin and the clock output is driven low during reset and by the SS (The subsystem selected with MUXMODE determines the output buffer state) after reset.
There are no PADCONFIG registers associated with the MMC0 pins.
The internal pulls associated with the MMC0 pins are dynamically controlled by the MMC0 host and PHY.
Provision for External pulls are not a requirement for the eMMC data, CMD, DS and the CLK signals.

2. Power supply and Sequencing 

The recommendation is to power the processor IO supply rail and the eMMC device from the same power source

3. Series resistor for eMMC clock output from the processor

it is  a good idea to place a series termination resistor as close as possible to the MMC0_CLK pin in case it is needed to dampen reflections caused by an impedance mismatch.

4.Series resistors for Data and command signals 

This is not a requirement. Optionally the series resistors can be included to  improve signal integrity and custom board design/layout dependent.

5. Calibration resistor 

Refer to the device specific data sheet for the recommendations including the resistor value.

6. Alternate Part recommendations

TI doesn't make specific component recommendations.
From the hardware perspective the MMC0 port on the AM6 devices are  compatible with the eMMC standards. So there should not be any hardware issue operating with any eMMC compliant device. See the MMC0 timing section of the datasheet for the eMMC data transfer modes supported.

7. Are these recommendations valid for AM64x

AM64X implements hard PHY similar to AM62P. AM62P and the general queries 2..6 can be followed.

8. Is the  reset ANDing logic for the device required and any recommendations?

The ANDing logic provides flexibility to reset the attached memory device. Refer SK schematics for implementation.
RESETSTATz output will satisfy the power-on and warm reset functions and can be used to reset the attached device. Ensure IO level compatibility between the RESETSTATz output and the attached device reset input. You will need a two input AND gate to insert the software controlled GPIO reset function for the case where software needs to initiate a reset to only
A pullup and an isolation resistor is recommended for the SoC IO output connected to the ANDing logic near to the AND gate.
When ANDing logic is not used, verify the IO compatibility of the SoC reset status output used and the attached memory device.

9. What is the default drive strength and can the drive strength be controlled?

These are typically about 40 ohms, but the customer should be using the IBIS model to determine the drive strength of the pins. 
The drive strength must remain in the default state since this is the only condition used during timing closure of the peripherals.

(+) [FAQ] AM62A7-Q1: SDIO driver strength change - Processors forum - Processors - TI E2E support forums

Drive strength is a function of changing the source impedance of an output buffer, where a lower source impedance results in a higher drive and a higher source impedance results in a lower drive. I would prefer to say we are changing source impedance rather than drive strength since this is what actually happens in the IO cell.

(+) [FAQ] AM62A7-Q1: SDIO driver strength change - Processors forum - Processors - TI E2E support forums

The AM62A7 eMMC port was timing closed with the default drive strength. Therefore, we do not recommend changing the drive strength since this could introducing signal timing issues with the attached eMMC device

We already know that; We will only try to change the drive strength. Please help share how to change?

Currently, there are no plans to support drive strength changes on the AM62Ax device.

Are there any suggestions to solve the problem of EMC-RE exceeding the standard caused by EMMC CLOCK?

You should investigate your PCB layout to determine why this signal is radiating. This typically occurs when there is a PCB trace impedance discontinuity, which also introduces signal distortion.
What does Sdhccore mean? How to understand?
This appears to be a reference to the MMCSD host controller, where it has the capability of changing the drive strength of output buffer to be one of the values defined in the eMMC standard. The output buffers being used to implement the AM62Ax eMMC port does not support all of the drive strengths defined in the eMMC standard. Therefore, the host controller drive strength control function is not implemented. The registers are there, but they have no impact on drive strength. The output buffer drive strength is fixed to 40 ohms.

Regards,

Sreenivasa

Regards,

Sreenivasa

Hi Board designers, 

Refer below FAQs:

Rise/Fall Time Requirement of MMC_CLK

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1483440/am623-rise-fall-time-requirement-of-mmc_clk/5696702

Hi Board designers, 

Refer below explanation regrading eMMC interface

The AM62x IOs associated with the MMC0 port will be turned off until software initializes them. This means any signals without internal pulls will be floating until software boots and initializes the IOs. The eMMC standard requires the eMMC device to have internal pulls on the DAT[7:1] pins, but the other pins do not have internal pulls. We recommend external pull-ups on the CMD and DAT0 signals and an external pull-down on the CLK signal. The eMMC standard also says 10k pull-ups are the min value, so we do not recommend using a 10k resistor because it may be less than 10k. We typically recommend using 47k resistors to minimize loading on the signals since the pulls are only used to hold the signals in a valid logic state when not driven. Therefore, I suggest changing the value of your pull resistors and installing the pullup for CMD.  I do not expect these changes to have any effect on the issue you are seeing, but these changes should be made to ensure long-term device reliability.

Regards,

Sreenivasa

Hi Board designers, 

Refer information related to eMMC clock:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1466492/faq-am625-is-the-emmc-clocks-maintained-when-read-and-write-operations-are-finished

I would like to know if the AM6352 continuously maintains the eMMC clock or if it stops it when it finishes the read and write processes.

Why asking ?
In most eMMC the “patrol” that refreshes and monitors the health of the memory works when it has the clock running.

If so, I was able to confirm the MMCSD host controller implemented in AM62x devices has the capability to pause the clock when there are no transfers, but that function is turned off by default.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1298166/am623-emmc-clock-output/4929951

The eMMC standard allows the host to stop the clock during read operations. The host controller implemented in AM62x uses this feature when the internal buffer is full. In these circumstances, the host controller will stop the clock in order to avoid buffer overrun condition.

Regards,

Sreenivasa

Hi Board designers, 

Additional references:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1089730/am4378-intermediate-potential/4041586

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1090498/am4378-intermediate-potential-during-reset

e2e.ti.com/.../2505155

Your first question cannot be answered without including actual PCB delays in any peripheral timing analysis.

There may be cases where a resistor/capacitor network can be used to delay a signal and help with timing, but this approach can be problematic. Inserting additional signal trace on the PCB to adjust timing may be a better approach. 

Timing requirements are given to the SOC design team and they make internal adjustments with the goal of meeting the requirements. The values provided are based on the respective peripheral industry standard, when applicable, and includes some assumptions about expected PCB trace delays. Once silicon is available, the product engineering team characterizes timing of the various peripherals. The data sheet values represent characterization data. 

In many cases there are trade-offs in a design that need to be considered and what must be done to benefit one function may compromising another. When this happens it may not be possible to meet all of our timing goals. So we publish the characterized values in the data sheet and leave some timing adjustments to the systems/PCB designer. 

This is why timing values may vary from one device to another. This is also the reason timing analysis should be performed on every peripheral using actual PCB delays. 

For the case mentioned in your E2E post, the effect of attached device min delay on the processor hold time should not be a problem since the processor to device clock delay and device to processor CMD/DAT delay will provide additional margin. However, the effect of processor min delay on the attached device hold time will be a problem if the system designer doesn’t insert at least 1.2ns additional delay on the CMD/DAT traces. 

Regards,

Sreenivasa

Hi Board designers, 

Information related to eMMC size

How much maximum memory size does AM6442 supports for eMMC memory?

There is no size limitation.  MMC0  (emmc controller) interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51)

I checked with the hardware and the software experts, and the answer is there are no limits or limitations.

Regards,

Sreenivasa

Hi Board designers, 

Information related to clock pulldown 

e2e.ti.com/.../faq-am625-what-s-the-purpose-for-the-pull-down-r-on-mmc_clk

May I know what the purpose for the pull down R on MMC_CLK signal on TI EVM? May I know what the purpose for the pull down R on MMC_CLK signal on TI EVM? 
Most of the IOs associated with the AM62x device default to the off state, which means any attached device input without an internal pull resistor would be floating until software configures the pin to drive the signal. We use an external pull-down rather than an external pull-up since the clock signal is held in a low logic state when paused.

 Because there are cases where the clock is stopped or paused in a low logic state and the pull-down option is consistent with this logic state.

(+) AM623: Problem Detecting eMMC at HS200 speed during 1.8V voltage switch. - Processors forum - Processors - TI E2E support forums

The effect you are describing by adding a series termination resistor seems to indicate a signal integrity issue. You mentioned testing modules. Does this mean the eMMC device is on a different PCB that the processor with eMMC host? If so, does your system maintain a constant signal trace impedance as the MMC0 signal transition across any board-to-board connector? Does any of your MMC0 signals cross split power/ground planes or transition from one reference plane to another such that a constant trace impedance is not maintained? 

Add a capacitor to any of the MMC0 signals can impact timing by slowing the signal transition relative to the other signals. This type of imbalance in signal load was not accounted for doing timing closure of the device. Getting improved results by adding a capacitor may indicate you have a timing issue in your system. It is acceptable to add capacitors as a debug step, but adding capacitors on the MMC0 signals should not be done in a production system. Did you ensure the signal trace delays in your system are within the limits defined in the datasheet MMC0 Timing Conditions table?

Regards,

Sreenivasa

Hi Board designers, 

Information related to clock measurement

What you observe on this signal depends on where you connected the probe, the bandwidth of your probe/scope, and quality of your scope probe ground. 

You will need a very high bandwidth probe and scope to observe short over-shoot, under-shoot, and non-monotonic events on the signal. I recommend using a low capacitance FET probe with a very-very short low loop inductance ground.

You will see a mid-supply step on the signal when probing near the source. This occurs because the output impedance of the MMC0_CLK output buffer, series termination resistor, and characteristic impedance of the PCB signal trace creates a voltage divider. The voltage divider output is applied to the source end of the PCB signal trace. This voltage propagates down the trace to the far end where it encounters a high impedance load which causes a in-phase reflection that returns to the source. Therefore, the voltage transition observed on the far end will be a continuous transition between VSS and VDD. The is not the case for the source end, as it steps to a mid-supply determined by the voltage divider values and the transition only continues to VDD or VSS once the reflection returns from the far end. You need to select a series resistor value that allows the MMC0_CLK pin to step through the voltage of (VDDSHV4 / 2) without pause. I suggest the step observed on the MMC0_CLK pin should be at least 200mv above (VDDSHV4 / 2) on the rising edge and at least 200mv below (VDDSHV4 / 2) on the falling edge.

Regards,

Sreenivasa

Hi Board designers, 

Information related to eMMC reset configuration 

[FAQ] AM62x: How to check and configure eMMC flash RST_N signal to support WARM_RESET from eMMC booting on AM62x-SK E2

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1168342/faq-am62x-how-to-check-and-configure-emmc-flash-rst_n-signal-to-support-warm_reset-from-emmc-booting-on-am62x-sk-e2

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1500901/tda4vm-this-is-a-question-about-emmc-boot/5769543

In case of eMMC ,reset can be done in 3 ways:

• CMD0
• HW_Reset
• Power cycle 

CMD0:(S/W RESET)

Sending CMD 0 with specfic arguments will do software reset of the eMMC .

H/W reset:

The h/w reset can be done by sending the RST_n signal .

By default, the RST_n signal is temporarily disabled in the dev

ice.
• The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

I am also attaching the JEDEC SPEC FOR EMMC which contains the details regarding resetting the eMMC which I would recommend going through:

JESD84-B51 (1).pdf

Hi Board designers, 

Information related to eMMC implementation for AM64x and AM62x

(39) SK-AM62: eMMC: Cannot write to MMCSD0_SS_PHY_CTRL_1/2/3 registers - Processors forum - Processors - TI E2E support forums

The MMC0 port on AM64x has a analog PHY with a DLL that is used to insert appropriate delays and controls most pin functions.  This port only supported eMMC signal functions operating at 1.8V.

The MMC1 port on AM64x uses a different method to insert delays and the IOs associated with this port are implemented with dual-voltage LVCMOS IO cells that were optimized for MMC/SD signal functions. This port supports multiple signal functions via pin multiplexing and they can operating at 1.8V or 3.3V.

The MMC0 port on AM62x is basically an 8-bit implementation of the AM64x and AM62x MMC1 port.

MMC0 on AM62x supports several eMMC and SD Card standards. Please refer to the MMCSD timing sub-section of the AM62x datasheet Timing and Switching Characteristics section for data transfer modes supported.

The MMC0 port does not provide the card detect and write protect inputs that would typically be connect to an SD Card connector. This port only supports SD Card data transfer modes to allow connectivity of embedded SDIO devices like WiFi. This port supports 1.8V or 3.3V, but 1.8V should be used in most cases since 1.8V provides more timing margin, which may be required for the faster data transfer modes.

The eMMC standard requires a device to provide internal pull-ups on DAT[7:1] by default.  These internal pull-up resistors will hold the DAT[7:1] signals in a valid logic state until the device is put into 4-bit or 8-bit mode, where the internal pull-ups are turned off on DAT[3:1] when placed in 4-bit mode or DAT[7:1] when placed in 8-bit mode. The AM62x internal pull-up resistors need to be turned on for the respective signals before the eMMC device is placed in 4-bit or 8-bit mode so signal are not allowed to float. A value of 0x60000 will turn on the AM62x internal pull-up and enable the input buffer for respective pins. 

We recommend an external pull-down resistor on CLK, and an external pull-up resistor on the DAT0 and CMD signals. This is required to hold these signals in a valid logic state since our IOs associated with these signals are off by default after power is applied, and the eMMC device does not have internal pulls on these pins. If you follow this recommendation, the internal pulls should remain off for each of these pins. A value of 0x40000 will turn on the internal pull-down and enable the input buffer on CLK. It is not clear why the internal pull-down and  input buffer is being turned on for CLK since we expect an external pull-down on this signal and the pin operates as an output only. As mentioned above a value of 0x60000 will turn on the AM62x internal pull-up and enable the input buffer for respective pins. So it is not clear why the internal pull-up is being turned on for DAT1 and CMD since we expect an external pull-up on these signals. 

I would not expect there to be an issue with turning on the input buffer for CLK, but it is not necessary.

I also do not expect an issue turning on internal pulls for signals with external pulls, as long as the external pulls are not in contention with the internal pulls and the total resistance doesn't go below the minimum pull resistance defined by the eMMC standard.

Regards,

Sreenivasa

Hi Board designers,

Inputs regarding HS200

(+) AM625: emmc HS200 Occasional IO errors - Processors forum - Processors - TI E2E support forums

The HS200 data transfer mode requires the read data path to be tuned for optimum timing. This means HS200 read timing varies based on the final tuning results. Therefore, it is not possible to define the device input requirements for HS200.

The eMMC standard requires an eMMC device to have internal pull-up resistors on DAT[7:1] turned on by default. The eMMC device will turn off the DAT[3:1] resistors once the device is switched to 4-bit mode, or will turn off the DAT[7:1] resistors once the device is switched to 8-bit mode. At this point the eMMC host must turn on its respective internal pull resistors, or external pulls must be used.

We require external pulls on the CLK, CMD, and DAT0 signals to hold the eMMC inputs in a valid logic state because the AM62x IOs are turned off by default. The eMMC device internal resistors will hold the DAT[7:1] inputs in a valid logic state until software has initialized the peripheral.

The eMMC boot code never enables the internal resistors on CLK, CMD, or DAT0 because they should already have external pulls as described above. However, it must turn on the AM62x DAT[7:1] internal resistors because the eMMC device will turn its internal resistors off once it enters 8-bit mode.

The pull resistance value of the AM62x internal pulls is defined in the SDIO Electrical Characteristics table found in the datasheet. The pull resistance value of the eMMC device internal pulls is defined in the eMMC standard. The pull resistance of the external pull resistors should be selected to be compliant to the eMMC standard.

FYI: There is an error in the eMMC Pin Usage table you inserted above. There is no pin named MMC0_CLKLB.

We recommend an external pull-down on CLK, an external pull-up on CMD, and an external pull-up on DAT0. The resistors values should be in the range of 15k to 50k ohms.

You only enable the AM62x internal pulls which are turned off in the eMMC device. The eMMC device will only turn off the DAT[3:1] resistors when the device is switched to 4-bit mode, so you would only need to turn on the AM62x internal pulls for DAT[3:1] when operating in 4-bit mode.  You would turn on the AM62x internal pulls for DAT[7:1] when operating in 8-bit mode.

The AM62x internal pulls are controlled via the respective PADCONFIG register.

Regards,

Sreenivasa