J7200XSOMXEVM: paired with the J721EXCP01EVM common processor board,Enable quad Ethernet daughter board

praveen kumar

Prodigy 60 points

Part Number: J7200XSOMXEVM

Hi,

I am trying out enable quad Ethernet daughter board which is expanded on top of carrier base board.

steps followed :

edit the uEnv.txt in boot partition of SD card with "names_overlays=quad-port-eth-exp.dtbo"

boot the board and end up with below error log.

U-Boot 2021.01-g62a9e51344 (May 02 2023 - 21:45:14 +0000)

SoC: J7200 SR2.0 GP
Model: Texas Instruments K3 J7200 SoC
Board: J7200X-PM2-SOM rev E8
DRAM: 4 GiB
Flash: 0 Bytes
MMC: sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In: serial@2800000
Out: serial@2800000
Err: serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
Detected: J7X-BASE-CPB rev A
Detected: J7X-VSC8514-ETH rev E2
Net: eth0: ethernet@46000000port@1
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
Failed to load 'boot.scr'
620 bytes read in 2 ms (302.7 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19655168 bytes read in 205 ms (91.4 MiB/s)
41354 bytes read in 3 ms (13.1 MiB/s)
3169 bytes read in 2 ms (1.5 MiB/s)
failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
base fdt does did not have a /__symbols__ node
make sure you've compiled with -@
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree

Could you please suggest how to load both dtb and dtbo so that firmware will pick both images and boot successfully .

Regards

Praveen

over 1 year ago

0 Tarun Mukesh Puvvada over 1 year ago

TI__Mastermind 38525 points

Hello,

Please expect delay in response since expert is out of office till tomorrow.

Regards

Tarun Mukesh

0 Diwakar Dhyani over 1 year ago in reply to Tarun Mukesh Puvvada

TI__Mastermind 47350 points

Hi Praveen

Title of the thread does not match with the problem detail provided above .

Can you please elaborate what exactly is the issue is it with the USB or with the quad Ethernet daughter board.

Regards
Diwakar

0 praveen kumar over 1 year ago in reply to Diwakar Dhyani

Prodigy 60 points

Hi Diwakar,

My apology for that , i created this ticket with wrong problem statement. not sure where to change this problem statement.

Yes, the issue with quad Ethernet daughter board.

Praveen

0 Diwakar Dhyani over 1 year ago in reply to praveen kumar

TI__Mastermind 47350 points

Hi Praveen

I updated the problem statement will re rout the question to the relevant expert allow some time to respond in this.

Regards
Diwakar

0 praveen kumar over 1 year ago in reply to Diwakar Dhyani

Prodigy 60 points

Okay, Thanks Diwakar.

-Praveen

0 Tanmay Patil over 1 year ago in reply to praveen kumar

TI__Mastermind 33980 points

Hi Praveen,

What is the SDK version you are using?

Are you using the default device-tree overlays or have you modified their names? If you are using defaut names, this is an incorrect name, "names_overlays=quad-port-eth-exp.dtbo". the name should be "name_overlays=k3-j7200-evm-quad-port-eth-exp.dtbo" for SDK 8.x and "name_overlays=ti/k3-j7200-evm-quad-port-eth-exp.dtbo" for SDK 9.0.

Also just pointing out that the property you were using was "names_overlays", it should be "name_overlays". Not sure if it was typo while copying or a mistake originally.

Regards,
Tanmay

0 praveen kumar over 1 year ago in reply to Tanmay Patil

Prodigy 60 points

Hi Tanmay,

Sorry it was just typo, in fact I am providing correct name in uEnv.txt like "name_overlays=k3-j7200-quad-port-eth-exp.dtbo".

Yes, i am trying out with default device tree overlay and SDK 8.x.

if you have close look at the log which i shared earlier , it is actually pass the files reading stage.

19655168 bytes read in 205 ms (91.4 MiB/s)
41354 bytes read in 3 ms (13.1 MiB/s)
3169 bytes read in 2 ms (1.5 MiB/s)

And all file size read are correctly.

Regards

Praveen

0 Tanmay Patil over 1 year ago in reply to praveen kumar

TI__Mastermind 33980 points

Hi Praveen,

Thanks for the clarification.

It seems you have built the base dts. Are there any changes in dts? Can you tell me the command you used to build it.

praveen kumar said:
failed on fdt_overlay_apply(): FDT_ERR_NOTFOUND
base fdt does did not have a /__symbols__ node
make sure you've compiled with -@

Can you also build the overlay and include this. There seems to be mismatch.

Regards,
Tanmay

0 praveen kumar over 1 year ago in reply to Tanmay Patil

Prodigy 60 points

Hi Tanmay,

command used to build both dtb and dtbo is "make dtbs"

and not done any changes on top of base dts files.

Regards

Praveen

0 Tanmay Patil over 1 year ago in reply to praveen kumar

TI__Mastermind 33980 points

Hi Praveen,

Shouldn't it be "make linux-dtbs"

This looks like some issue with compiling dtbs maybe. I will forward this question to the relevant expert. Please expect a response in couple of days.

Regards,
Tanmay

0 praveen kumar over 1 year ago in reply to Tanmay Patil

Prodigy 60 points

Hi Tanmay,

I don't think issue with compiling dtbs , because i tried by concatenating both dtb and dtbo manually with fdtoverlay tool and generated final dtb which loaded successfully, but when try to load both dtb and dtbo binaries separately through uEnv.txt by which i am facing the issue.

Regards

Praveen

0 Keerthy J over 1 year ago in reply to praveen kumar

TI__Guru**** 155150 points

Hi Praveen,

Please share the base dts file and also the overlay source file. It seems that some dependency is not met correctly. Also can you try comparing with the default ones that work straight out of the SDK and see if there's something missing in your dts source files.

Best Regards,

Keerthy

0 praveen kumar over 1 year ago in reply to Keerthy J

Prodigy 60 points

Hi Keerthy,

Attached requested files.

Note files are renamed as below to satisfy uploading requirements.

k3-j7200-common-proc-board.dts -> k3-j7200-common-proc-board.txt

k3-j7200-som-p0.dtsi -> k3-j7200-som-p0.txt

k3-j7200-quad-port-eth-exp.dts -> k3-j7200.quad-port-eth-exp.txt

Regards

Praveen

k3-j7200-common-proc-board.txt

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	cpsw5g_virt_mac: main_r5fss_cpsw5g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			/* local-mac-address = [0 0 0 0 0 0]; */
		};
	};

	cpsw9g_virt_maconly: main-r5fss-cpsw9g-virt-mac1 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethmac-device-1";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			/* local-mac-address = [0 0 0 0 0 0]; */
		};
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		/* Output of TPS22918 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv: gpio-regulator-TLV71033 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};
};

&wkup_pmx2 {
	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
		>;
	};
};

&main_pmx0 {
	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
		>;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
		>;
	};
};

&main_pmx1 {
	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
		>;
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "reserved";
};

&main_uart0 {
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart2 {
	/* MAIN UART 2 is used by R5F firmware */
	status = "reserved";
};

&main_uart3 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart4 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart5 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart6 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart7 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart8 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&wkup_gpio1 {
	status = "disabled";
};

&main_spi4 {
	status = "disabled";
};

&mcu_spi0 {
	status = "disabled";
};

&mcu_spi1 {
	status = "disabled";
};

&mcu_spi2 {
	status = "disabled";
};

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
};

&davinci_mdio {
	bus_freq = <20000>;

	phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

/*
 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
 * swapped on the CPB.
 *
 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
 */
&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
	};
};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD card */
	pinctrl-0 = <&main_mmc1_pins_default>;
	pinctrl-names = "default";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&serdes_ln_ctrl {
	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
};

&usb_serdes_mux {
	idle-states = <1>; /* USB0 to SERDES lane 3 */
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
	ti,usb2-only;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "high-speed";
};

&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&serdes_refclk {
	clock-frequency = <100000000>;
};

&serdes0 {
	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};

	serdes0_qsgmii_link: phy@1 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz0 3>;
	};
};

&cpsw0 {
	/* Disable cpsw0 since cpsw5g_virt_mac is the default Ethernet
	 * controller. cpsw0 is enabled with overlay for native
	 * Ethernet driver support
	 */
	status = "disabled";
};

&pcie1_rc {
	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

&pcie1_ep {
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
	status = "disabled";
};

&wkup_i2c0 {
	status = "okay";
	tps6594x: tps6594x@48 {
		compatible = "ti,tps6594x";
		reg = <0x48>;
		ti,system-power-controller;

		rtc {
			compatible = "ti,tps6594x-rtc";
		};

		gpio {
			compatible = "ti,tps6594x-gpio";
		};
	};
/* I2C endpoint device: an Atmel EEPROM */
                eeprom@50 {
                    compatible = "atmel,24c256";
                    reg = <0x50>;
                    pagesize = <64>;
                };

};

k3-j7200-som-p0.txt

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j7200.dtsi"

/ {
	memory@80000000 {
		device_type = "memory";
		/* 4G RAM */
		reg = <0x00 0x80000000 0x00 0x80000000>,
		      <0x08 0x80000000 0x00 0x80000000>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>;
			alignment = <0x1000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a4000000 {
			reg = <0x00 0xa4000000 0x00 0x00800000>;
			alignment = <0x1000>;
			no-map;
		};

		main_r5fss0_core0_shared_memory_queue_region:r5f-virtual-eth-queues@a5000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5000000 0x00 0x200000>;
			no-map;
		};

		main_r5fss0_core0_shared_memory_bufpool_region:r5f-virtual-eth-buffers@a5200000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5200000 0x00 0x1e00000>;
			no-map;
		};

	};
};

&wkup_pmx0 {
	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
		>;
	};

	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
		>;
	};
};

&main_pmx0 {
	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
		>;
	};
};

&hbmc {
	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
	 * appropriate node based on board detection
	 */
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */

	flash@0,0 {
		compatible = "cypress,hyperflash", "cfi-flash";
		reg = <0x00 0x00 0x4000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "hbmc.tiboot3";
				reg = <0x0 0x100000>;
			};

			partition@100000 {
				label = "hbmc.tispl";
				reg = <0x100000 0x200000>;
			};

			partition@300000 {
				label = "hbmc.u-boot";
				reg = <0x300000 0x400000>;
			};

			partition@700000 {
				label = "hbmc.env";
				reg = <0x700000 0x40000>;
			};

			partition@800000 {
				label = "hbmc.rootfs";
				reg = <0x800000 0x3800000>;
			};
		};
	};
};

&mailbox0_cluster0 {
	interrupts = <436>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster1 {
	interrupts = <432>;

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster2 {
	status = "disabled";
};

&mailbox0_cluster3 {
	status = "disabled";
};

&mailbox0_cluster4 {
	status = "disabled";
};

&mailbox0_cluster5 {
	status = "disabled";
};

&mailbox0_cluster6 {
	status = "disabled";
};

&mailbox0_cluster7 {
	status = "disabled";
};

&mailbox0_cluster8 {
	status = "disabled";
};

&mailbox0_cluster9 {
	status = "disabled";
};

&mailbox0_cluster10 {
	status = "disabled";
};

&mailbox0_cluster11 {
	status = "disabled";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&mcu_r5fss0_core1 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
			<&mcu_r5fss0_core1_memory_region>;
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>,
			<&main_r5fss0_core0_shared_memory_queue_region>,
			<&main_r5fss0_core0_shared_memory_bufpool_region>;
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp_som: gpio@21 {
		compatible = "ti,tca6408";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
				  "GPIO_LIN_EN", "CAN_STB";
	};
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi.tiboot3";
				reg = <0x0 0x100000>;
			};

			partition@100000 {
				label = "ospi.tispl";
				reg = <0x100000 0x200000>;
			};

			partition@300000 {
				label = "ospi.u-boot";
				reg = <0x300000 0x400000>;
			};

			partition@700000 {
				label = "ospi.env";
				reg = <0x700000 0x40000>;
			};

			partition@740000 {
				label = "ospi.env.backup";
				reg = <0x740000 0x40000>;
			};

			partition@800000 {
				label = "ospi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "ospi.phypattern";
				reg = <0x3fc0000 0x40000>;
			};
		};
	};
};

k3-j7200-quad-port-eth-exp.txt

// SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
 * J7200 board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@101 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;
};

&cpsw0_port1 {
	phy-handle = <&cpsw5g_phy0>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>;
};

&cpsw0_port2 {
	phy-handle = <&cpsw5g_phy1>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw0_port3 {
	phy-handle = <&cpsw5g_phy2>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 3>;
};

&cpsw0_port4 {
	phy-handle = <&cpsw5g_phy3>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 4>;
};

&cpsw5g_mdio {
	bus_freq = <1000000>;
	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw5g_phy0: ethernet-phy@16 {
		reg = <16>;
	};
	cpsw5g_phy1: ethernet-phy@17 {
		reg = <17>;
	};
	cpsw5g_phy2: ethernet-phy@18 {
		reg = <18>;
	};
	cpsw5g_phy3: ethernet-phy@19 {
		reg = <19>;
	};
};

&cpsw5g_virt_mac {
	status = "disabled";
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio0_pins_default: mdio0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
			J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
			J721E_IOPAD(0x168, PIN_OUTPUT, 1) /* (U21) MCAN16_RX.CLKOUT */
		>;
	};
};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};

0 Keerthy J over 1 year ago in reply to praveen kumar

TI__Guru**** 155150 points

Praveen,

Have you compared this with the working files on the EVM? Have you changed anything in the source dts files?

Best Regards,

Keerthy

0 praveen kumar over 1 year ago in reply to Keerthy J

Prodigy 60 points

Hi Keerthy,

I could see some difference w.r.t address under wkup_pmx2 node,attached snapshot for your reference (Left side file from TI SDK ) ,

i tried incorporating these changes but dhcp request fails during boot-up , attached snapshot for your reference.

Regards

Praveen

0 Keerthy J 11 months ago in reply to praveen kumar

TI__Guru**** 155150 points

Hi,

Those are pin mux changes that can potentially impact CPSW i.e ethernet. So on your custom board the pin mux will be different I believe.
Are you seeing issues with that as well?

- Keerthy

0 praveen kumar 11 months ago in reply to Keerthy J

Prodigy 60 points

Hi Keerthy,

If i don't incorporate the changes which are from TI SDK and retain the as per TI git branch, ETH port is working fine and don't see any issue.

Regards

Praveen

0 Keerthy J 11 months ago in reply to praveen kumar

TI__Guru**** 155150 points

Hi Praveen,

Please share delta that causes the issue. I will review it. So if I understood correctly you have a working combination now?

Best Regards,

Keerthy

0 praveen kumar 11 months ago in reply to Keerthy J

Prodigy 60 points

Hi Keerthy,

Looks like some confusion here, let me reiterate the issue.

Actually the real issue is to enable the ETH quad extension port which consist of total 4 ETH (QSGMII) port which normally done with the help of overlay device tree source (k3-j7200-quad-port-eth-exp.dts) which is available. so now the question is how to apply these overlay changes to final dtb , so i followed the procedure which TI docs briefs like adding ""name_overlays=k3-j7200-quad-port-eth-exp.dtbo" in uEnv.txt so that u-boot will parse and pick it and apply on top of base dtb changes. but in my case i am end up with below boot up log error

U-Boot 2021.01-g62a9e51344 (May 02 2023 - 21:45:14 +0000)

And now the delta which you are asking purely for CPSW i.e ethernet as you mentioned in earlier mail , so i think these delta changes we can ignore because CPSW port is working fine for me . Hope you got some clarity now.

Regards

Praveen

0 Keerthy J 11 months ago in reply to praveen kumar

TI__Guru**** 155150 points

Hi Praveen,

=> setenv name_overlays k3-j7200-evm-quad-port-eth-exp.dtbo
=>
=> boot
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
Failed to load 'boot.scr'
57 bytes read in 7 ms (7.8 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
19640832 bytes read in 212 ms (88.4 MiB/s)
59640 bytes read in 10 ms (5.7 MiB/s)
Working FDT set to 88000000
3263 bytes read in 9 ms (353.5 KiB/s)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Working FDT set to 88000000
Loading Device Tree to 000000008feee000, end 000000008fffffff ... OK
Working FDT set to 8feee000

I see no issues when i do from the command prompt.

Please try to match the dtbo names exactly. I am trying on 9.0 SDK on J7200 EVM.

- Keerthy

0 praveen kumar 11 months ago in reply to Keerthy J

Prodigy 60 points

Hi Keerthy,

Thanks for your inputs.

Yes, by setenv overlay_name through command prompt its working for me as well. is there is reason why it is not picking automatically by parsing uEnv.txt by the u-boot code? is there any specific u-boot source need to be used where this issue is not seen?

Regards

Praveen

0 Keerthy J 11 months ago in reply to praveen kumar

TI__Guru**** 155150 points

Praveen,

So for now can you use the setenv command while we try to check why uEnv.txt is not helping? Are you unblocked for now?

- Keerthy

0 praveen kumar 11 months ago in reply to Keerthy J

Prodigy 60 points

Hi Keerthy,

Yes, with your suggested procedure we are unblocked now , it would be good if you come up with solution for auto picking overlay through uEnv.txt.

Regards

Praveen

0 Keerthy J 11 months ago in reply to praveen kumar

TI__Guru**** 155150 points

Praveen,

For using uEnv.txt instead of:

setenv name_overlays k3-j7200-evm-quad-port-eth-exp.dtbo

Just use

name_overlays=k3-j7200-evm-quad-port-eth-exp.dtbo

I checked internally and the works.

Can you try this?

Best Regards,

Keerthy

Processors

Processors forum

J7200XSOMXEVM: paired with the J721EXCP01EVM common processor board,Enable quad Ethernet daughter board