Other Parts Discussed in Thread: SYSCONFIG, DRA821
Tool/software:
Dear Sir/ Madam,
I am using DRA821U as a gateway controller in my design, and I have below questions need your confirmation.
1. For SerDes0 and CPSW5G, can below configurations be run at the same time? I have this question because there is notes on DRA821 TRM Page 37 saying that A maximum of two of the three IP can be used concurrently. But, by using TI PinMux tool SysConfig, there is no warning or error messages shown when below configurations were made.
SerDes0 Lane0 - PCIe Lane0 (PCIe x1 Lane Mode)
SerDes0 Lane1 - SGMII Lane4 (CPSW5 Port 4, SGMII Interface)
SerDes0 Lane2 - SGMII Lane1 (CPSW5 Port 1, SGMII Interface)
SerDes0 Lane3 - USB3 (USB3.0)
RGMII2 (CPSW5 Port 2, RGMII Interface)
RGMII3 (CPSW5 Port 3, RGMII Interface)
2. For SerDes0 USB Application, TRM Page 958, 5.1.3.4.27, Table 5-749, SERDES_SEL Register bit says USB3.0 interface can be 2 different SERDES0 lanes, options are Ln1 and Ln3, but in SysConfig, Ln0 and Ln2 can also be selected without any warning or error messages. Please make clarifications.
3. For SerDes0 Lane0 used as PCIe, can it support PCIe 1.1?