Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hi,
it seems like the cpsw and mdio association is this one:
main_cpsw0 <-> MDIO1 PINS
main_cpsw1 <-> MDIO0 PINS
I discovered it experimentally and found something in this file: arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
&main_pmx0 {
mdio0_pins_default: mdio0-pins-default {
pinctrl-single,pins = <
J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
>;
};
};
&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
Can TI confirm this? Is it documented?
Currently, I am activating cpsw0 and I cannot see any clock on MDIO0_MDC, while, if I configure MDIO1_MDC pinmux, I can see the clock (1MHz).