Tool/software:
Hi expert,
Our customer finds A72 will impact the cycle time of MCU21. They want to set the DDR access priority of MCU2_1 to avoid A72 impact. So they refer to below thread and TDA4VMid sdk, adding the QoS setting as below.
But they run into questions that need to be checked:
1. They found the variables QOS_R5FSS1_CORE0_MEM_RD_ATYPE and QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID are not defined in the setup_main_r5f1_qos_api. Can they use the definition in QOS_R5FSS0 directly?
2. They read back and found below register is still 0?
3. QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP is for MCU3_0?
void SBL_SetQoS()
static void J721E_SetupQoS()
{
setup_navss_nb();
setup_c66_qos();
/* Workaround to unblock PDK-8359 .
* setup_main_r5f_qos() results in crashing the UDMA DRU examples on
* mcu2_0(with SBL uart boot mode) during CSL_REG64_WR(&pRegs->DRUQueues.CFG[queueId], regVal);
* Hence commenting out the following. */
setup_main_r5f_qos();
setup_vpac_qos();
setup_dmpac_qos();
setup_dss_qos();
setup_gpu_qos();
setup_encoder_qos();
setup_compute_cluster_qos();
setup_mcu_r5f_qos();
setup_main_r5f1_qos();
}
/* NAVSS North Bridge (NB) */
#define NAVSS0_NBSS_NB0_CFG_MMRS 0x3802000
#define NAVSS0_NBSS_NB1_CFG_MMRS 0x3803000
#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
void setup_navss_nb(void)
{
/* Map orderid 8-15 to VBUSM.C thread 2 (real-time traffic) */
CSL_REG32_WR(NAVSS0_NBSS_NB0_CFG_NB_THREADMAP, 2);
CSL_REG32_WR(NAVSS0_NBSS_NB1_CFG_NB_THREADMAP, 2);
}
#define QOS_R5FSS1_CORE0_MEM_RD 0x45d85000
#define QOS_R5FSS1_CORE0_MEM_RD_NUM_J_CH 3
#define QOS_R5FSS1_CORE0_MEM_RD_NUM_I_CH 1
#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP1(j) (QOS_R5FSS1_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP2(j) (QOS_R5FSS1_CORE0_MEM_RD + 0x4 + (j) * 8)
#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(i) (QOS_R5FSS1_CORE0_MEM_RD + 0x100 + (i) * 4)
#define QOS_R5FSS1_CORE0_MEM_WR 0x45d85800
#define QOS_R5FSS1_CORE0_MEM_WR_NUM_J_CH 3
#define QOS_R5FSS1_CORE0_MEM_WR_NUM_I_CH 1
#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP1(j) (QOS_R5FSS1_CORE0_MEM_WR + 0x0 + (j) * 8)
#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP2(j) (QOS_R5FSS1_CORE0_MEM_WR + 0x4 + (j) * 8)
#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(i) (QOS_R5FSS1_CORE0_MEM_WR + 0x100 + (i) * 4)
#define QOS_R5FSS1_CORE0_MEM_RD_PRIORITY (2U)
#define QOS_R5FSS1_CORE0_MEM_WR_PRIORITY (2U)
void setup_main_r5f1_qos(void)
{
unsigned int channel, group;
/* R5FSS1 core0 - read */
for (group = 0; group < QOS_R5FSS1_CORE0_MEM_RD_NUM_J_CH; ++group)
{
CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
}
for (channel = 0; channel < QOS_R5FSS1_CORE0_MEM_RD_NUM_I_CH; ++channel)
{
CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(channel), (QOS_R5FSS1_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS1_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4));
}
/* R5FSS1 core0 - write */
for (group = 0; group < QOS_R5FSS1_CORE0_MEM_WR_NUM_J_CH; ++group)
{
CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
}
for (channel = 0; channel < QOS_R5FSS1_CORE0_MEM_WR_NUM_I_CH; ++channel)
{
CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(channel), (QOS_R5FSS1_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS1_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4));
}
}
Best Regards,
Xingyu Zhu
