Other Parts Discussed in Thread: DRA829,
Tool/software:
Hi TI-team,
Searching for a reason why I get an NMI within C66xx_0 core I found in sprugw0c.pdf (TMS320C66xDSP_CorePac) in Figure 9-1 or Fig. 9-11 or Fig. 9-14 that an
"outside the core" event "NMEVT" can trigger an NMI (of C66x).
But these three are the only occurrences of "NMEVT" within:
- sprugw4a.pdf (KeyStone_ChipInterruptController_UserGuide)
- sprugw0c.pdf (TMS320C66xDSP_CorePac)
- sprui04f.pdf (C6x_ OptimizingCompiler v8_3_x)
- sprui03e.pdf (TMS320C6000_AssemblyLanguageTools)
- sprugh7.pdf (TMS320C66x_CPUandInstructionSetReferenceGuide)
- SPRUIL1B.pdf (J721E TDA4VM,DRA829 Processors Silicon Revison 1.1 TRM)
- spruil1c.pdf (J721E TDA4VM,DRA829 Processors Silicon Revison 1.1 TRM)
- J721E_registers1.pdf ... J721E_registers5.pdf
Could someone tell me:
- Who can trigger "NMEVT"?
- Is there a list of trigger reasons for NMI / NMEVT?
(except the SWE / SWENR instruction)
Thanks in advance, Wolfgang
P.S.: NMI is received after excecution from:
Board_init(boardCfg);
-- within this from.:
if (cfg & BOARD_INIT_PINMUX_CONFIG)
ret = Board_pinmuxConfig();
-- within this from::
Board_STATUS Board_pinmuxUpdate (pinmuxBoardCfg_t *pinmuxData, uint32_t domain)
It seems the SCI_client function is "responsible". It is only received once after power up, disregarding reset & restart of C66x_0. Hence, I suppose it's from SCI_server on MCU_Cortex_R5_0.
P.P.S.: As of "TMS320C66x CPU and Instruction Set Reference" 7.1.1.2 Nonmaskable Interrupt (NMI)
"NMI ... is generally used to alert the CPU of a serious hardware problem" - Hence, my concern.