Tool/software:
Hi, support.
I have two questions about GPMC.
1. Can I read/write and boot from NAND Flash using GPMC with PSDK9.1.0.8?
2. What is the operating clock of the GPMC? And how can I check it? I need it to calculate the write/read timing.
The operating environment is as follows.
EVM: TMDS64EVM (connecting to custom NAND board from HSC)
PSDK: 9.1.0.8
Best Regards,
TO
Hello Anil,
Thank you for your support.
There's no problem with the GPMC timing.
The connection between the AM64EVM and the NAND Flash is too long, so waveform is noisy.
Therefore, I determined it was a hardware problem.
Could you please tell me one more thing?
I have a question regarding NAND write timing waveforms.
1. What is happening during the period indicated by the red arrow below? CS is deassertion.
2. I want to eliminate this period, but how can I do it?
* In the image below, the yellow arrow is "CS", the pink arrow is "WE", and the blue arrow is "D0".
Reference
1. The register values when checking the waveform are as follows:
GPMC_CONFIG1_0(0x3B000060) : 0x00000800
GPMC_CONFIG2_0(0x3B000064) : 0x00060700
GPMC_CONFIG3_0(0x3B000068) : 0x00040400
GPMC_CONFIG4_0(0x3B00006C) : 0x03000501
GPMC_CONFIG5_0(0x3B000070) : 0x00050607
GPMC_CONFIG6_0(0x3B000074) : 0x86000000
GPMC_CONFIG7_0(0x3B000078) : 0x00000F51
2. NAND read timing is fine
CS is never deasserted while reading data.
* In the image below, the yellow arrow is "CS", the pink arrow is "RE", and the blue arrow is "D0".
Best Regards,
TO
Hello Anil,
Thank you for your response.
Could you please answer the following questions 1 and 2?
I have a question regarding NAND write timing waveforms.
1. What is happening during the period indicated by the red arrow below? CS is deassertion.
2. I want to eliminate this period, but how can I do it?
* In the image below, the yellow arrow is "CS", the pink arrow is "WE", and the blue arrow is "D0".
Best Regards,
TO
Hello TO,
In the above GPMC tool.
You can go through the NAND Timings tab.
Then, go for the NAND command latch cycle in which you can check for tCH parameter.
I have given a 5nsec value based on the NAND datasheet which we connected to EVM.
In your case, go through the datasheet and feed the minimum value on the Excel sheet and later try to modify only the CSWROFFTIME parameter.
In MCU+SDK we default configured to 6, then after updating according to the NAND datasheet, we can make it 4 as well.
The 4 value is followed by both tCH minimum and maximum criteria.
After updating the change , please confirm both read and write cycles .
Regards,
Anil.
Hello Anil,
I changed CSWROFFTIME to 4clock and confirmed the NAND write waveform. It is as follow image:
However, the red arrow period did not eliminate. There seems to be a blank period of about 100ns after writing two bytes.
I have a question about this period marked with a red arrow.
1.Is it possible to eliminate this period?
2.What is GPMC driver doing this period?
Best Regards,
TO
Hello, Mark,
Thank you for your confirmation.
K3 devices cannot use DMA for GPMC access, so does this mean that AM64xx cannot eliminate the period indicated by the red arrow below?
I have a question about this period marked with a red arrow.
1.Is it possible to eliminate this period?
2.What is GPMC driver doing this period?
Regards,
TO
Hello TO/Mark,
In MCU+SDK on R5F cores, we do support DMA on the Read cycle.
Please look at the image below, there is NAND FIFO, and it is filled after 64 bytes and it generates one event. That event can trigger DMA.
I assume that DMA is also possible in write cycles.
So, AM64X devices GPMC support DMA for NAND GPMC devices.
I do not understand why the above delay is in the Write cycle rather than the read cycle.
Regards,
Anil.
