TDA4VP-Q1: PCIe Interface and Clock

Hi Ratheesh,

ratheesh chandran said:

Can we configure this SERDES0 as 2 x 2L

Yes, please reference this SERDES documentation in SDK for more information about limitations: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/10_00_00_08/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/SERDES/SERDES.html

ratheesh chandran said:

If SoC configured as Root complex do we need to supply the clock? Or it can be supplied internally by PLL.

Yes, it is possible to choose one or the either. On J784S4 EVM, one PCIe port is connected to an external clock supply, while the other provides internal SERDES clock out to connector. Please reference the "Design files" for the schematics for J784S4 EVM: https://www.ti.com/tool/J784S4XEVM

ratheesh chandran said:

If SoC configured as Endpoint do we need to supply the clock? or it can be supplied internally.

Either is fine. We provide a demo for configuring as EP and it can be used regardless of using an external clock supply or internal PLL clock: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/10_00_00_08/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_End_Point.html. 

ratheesh chandran said:

If clock has to be applied to which pins do we need to apply the clock? SERDES0_REFCLK_x or PCIE_REFCLK1_x_OUT ?

I would again recommend the "Design files" for a reference.

Regards,

Takuma