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TDA4VM: Query Regarding DDR Bank Interleaving Support on TDA4VM (J721E)

Amarnath MB
Prodigy 30 points
Part Number: TDA4VM

Tool/software:

Hello TI Support Team,

I am currently working with the TDA4VM and would like to understand if it supports interleaving of banks within the DDR. While the feature is mentioned as one of the key capabilities of the DDR subsystem in the reference manual (8.2.1 DDRSS Overview), I couldn’t find detailed information or configuration steps. There isn’t any specific option to enable or configure DDR bank interleaving in the provided DDR configuration tool. The only relevant option I found is 'Multi DDRSS Interleave Hybrid Config,' which is set to 'Interleave Only,' but it is greyed out.

Specifically, I have the following questions:

  1. Does the TDA4VM support DDR bank interleaving?
  2. If supported, how can it be enabled or configured?
  3. Is there a specific option available for this in the DDR configuration tool? If not, are there other steps required (e.g., register settings)?

Any additional guidance or documentation related to this would be highly appreciated.

Thank you in advance for your assistance

Regards,

Amar

  • +1
    TI__Mastermind 33615 points

    Hi,

    Amarnath MB said:
    The only relevant option I found is 'Multi DDRSS Interleave Hybrid Config,' which is set to 'Interleave Only,' but it is greyed out.

    This doesn't apply to TDA4VM. This parameter is related to TI devices which have multiple DDR sub-systems, but TDA4VM only has 1 DDR sub-system.

    Amarnath MB said:
    Does the TDA4VM support DDR bank interleaving?

    Bank interleaving is supported within rows of the DDR memory, meaning that the row address is higher order than the bank address.

    Amarnath MB said:
    If supported, how can it be enabled or configured?

    There is no way to enable it (or disable it). The row address is always higher order than the bank address.

    Regards,
    Kevin