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TDA4AL-Q1: TDA4AL DDR

andy shi
Prodigy 80 points
Part Number: TDA4AL-Q1
Other Parts Discussed in Thread: DRA821

Tool/software:

We are currently configuring DDR parameters, where DDRSS_PLL_FHS_CNT is set to 10 on the J721E platform and 5 on the J721S2 platform. On the tda4al platform, we are using Hynix DDR and encountered bit flips when configured to 4266MHz. After changing DDRSS_PLL_FHS_CNT to 10, the system became stable. Could you please explain why the values of DDRSS_PLL_FHS_CNT differ between these two platforms, and what impact DDRSS_PLL_FHS_CNT has?

  • 0
    TI__Mastermind 32705 points
    andy shi said:
    Could you please explain why the values of DDRSS_PLL_FHS_CNT differ between these two platforms,

    DDRSS_PLL_FHS_CNT defines the number of times the DDR PHY will request the CPU to change the DDR PLL frequency. The DDR PHY requests a DDR PLL frequency change during command bus training of the LPDDR4 memory. This process (changing frequency during command bus training) is a JEDEC standard and is typically described in memory vendor's LPDDR4 datasheets.

    The value assigned to DDRSS_PLL_FHS_CNT by the DDR register configuration tool is determined by the number or RANKS of the LPDDR4 memory, as well as how many "frequency sets" are enabled. 

    The difference between J721E and J721S2 is that we disabled one of the frequency sets to improve boot time. Because there is half as many frequency sets enabled on J721S2 compared to J721E, the number of frequency changes is cut in half. This change is documented in the register configuration tool revision history.

    v0.10.0, item #3

    3) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
        - NOTE: This update applies the changes from item number 8 from v0.8.0 of the tool to J721S2 devices.
        - Global and Register Updates
            > See description of item number 8 from v0.8.0 of the tool.

    v0.8.0, item #8

    8) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
        - NOTE: These changes only apply to DRA821
        - Global Updates
            > Updated calculation of macro DDRSS_PLL_FHS_CNT
        - Register Updates (impacted parameters)
            > DDRSSn_PI_12, PI_FREQ_MAP
            > DDRSSn_PI_13, PI_INIT_WORK_FREQ
            > DDRSSn_PI_176, PI_WRLVL_EN_F2
            > DDRSSn_PI_182, PI_RDLVL_GATE_EN_F2
            > DDRSSn_PI_182, PI_RDLVL_EN_F2
            > DDRSSn_PI_191, PI_CALVL_EN_F2
            > DDRSSn_PI_217, PI_WDQLVL_EN_F2

    andy shi said:
    After changing DDRSS_PLL_FHS_CNT to 10, the system became stable.

    The value of DDRSS_PLL_FHS_CNT needs to be in sync with the rest of the register settings. If you just changed DDRSS_PLL_FHS_CNT from 5 to 10 but register settings only enable 1 frequency set, then software would be waiting in a "for" loop for frequency change requests that the DDR PHY never requests. So I assume you are using the J721E configuration file entirely, and didn't just change DDRSS_PLL_FHS_CNT. There are likely other difference between the configuration files related to your observations.

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 80 points

    Hi Kevin

    Thanks for your reply. You are right, We are currently using all the DDR settings for J721E. Could you help analyze why there are such differences between these two sets of DDR parameter settings on TDA4al?

    Thanks,

    Andy

  • 0 in reply to Kevin S
    Intellectual 325 points

    Hi Kevin:

                  Is there any relationship between the value DDRSS_PLL_FHS_CNT and training? Does the size of this value affect the training time?

  • 0 in reply to Gaston yan
    TI__Mastermind 32705 points

    Hi,

    Gaston yan said:
     Is there any relationship between the value DDRSS_PLL_FHS_CNT and training? Does the size of this value affect the training time?

    A larger DDRSS_PLL_FHS_CNT value implies more ranks / "frequency sets" are enabled. Thus, more training is required, impacting the training / initialization time.

    Please see the original post (copied below) which gives more detail:

    Kevin S said:

    DDRSS_PLL_FHS_CNT defines the number of times the DDR PHY will request the CPU to change the DDR PLL frequency. The DDR PHY requests a DDR PLL frequency change during command bus training of the LPDDR4 memory. This process (changing frequency during command bus training) is a JEDEC standard and is typically described in memory vendor's LPDDR4 datasheets.

    The value assigned to DDRSS_PLL_FHS_CNT by the DDR register configuration tool is determined by the number or RANKS of the LPDDR4 memory, as well as how many "frequency sets" are enabled. 

    The difference between J721E and J721S2 is that we disabled one of the frequency sets to improve boot time. Because there is half as many frequency sets enabled on J721S2 compared to J721E, the number of frequency changes is cut in half.

    Regards,
    Kevin