TMS320C6657: SRIO boot with DDR configuretion table

Dear Customer

?? ? said:

1. Can adding a DDR configuration table to the srio boot table initialize DDR during the SRIO boot and then write the. text segment to DDR.

Yes. That's right

?? ? said:

2. If the technical solution for problem one is feasible, does it only need to write the content of emif4Cfg to 0x008ffd20 during the initialization process using the DDR configuration table in the srio boot? Do I need to write certain registers to trigger DDR initialization?

Writing the content of emif4Cfg is enough for DDR configuration.

Regards

Shankari G

Hi Shankari G

In my understanding, writing emif4Cfg is enough too.

However, in actual operation, after writing emif4Cfg to 0x008ffd20, I checked the DDR3 memory controller Register value by connecting to DSP via JTAG and found that DDR was not initialized properly. Even these registers remain unchanged.These registers of DDR3 did not initialize successfully through the DDR3Init() function like the platform lib evm6657l provided in the packages.

In my understanding, if I configure emif4Cfg with different values, the values of DDR3 registers should change. So I added different emif4Cfg to the srio boot image and should be able to see the register initialized to different values, but in reality, I didn't see any changes in the DDR3 register values. Does this mean that the emif4Cfg I wrote in did not work?

Can you provide guidance to help me investigate why emif4Cfg is not effective?

Thank you.

Dear Customer

?? ? said:

, I didn't see any changes in the DDR3 register values. Does this mean that the emif4Cfg I wrote in did not work?

Probably, Yes.

Because, when we execute the direct SPI boot, visualize the DDR3 registers using CCS.

Particularly before and after the emif4Cfg write.

?? ? said:

Can you provide guidance to help me investigate why emif4Cfg is not effective?

Sure. Follow the debug technique of visualizing the emif4Cfg using CCS.

Using CCS, debug the spiboot.c and observe the values getting updated after running the spiboot.c

Follow this method in your setup and visualize the configuration before and after your "emif4Cfg written"

I hope you get what I say.

Regards

Shankari G

Hi Shankari G

I conducted some tests based on your suggestion.

1 create an new empty ccs project,  Add in spiboot releated download from:

e2e.ti.com/.../0435.C6657_5F00_directROM_5F00_Boot_5F00_example.zip

I see there is no emif4Cfg in map file, so I changed project build->C6000 Linker->Advanced Options->Miscellaneous ->Eliminate section not need in the executable as off

2 change emif4Cfg value:

first I use platform lib func to init DDR, and then upload DDR3 MEMORY controller registers val.

according thes value to changed  emif4Cfg;

so I got a new emif4Cfg table, after rebuild it, and then load this project to dsp, ccs report verify error, which mean ddr3 still not init correct.

3 i upload ddr3 register2 val, campared with normal inited , it same emif4Cfg is not working

resource share:
normal ddr register2 upload val:

DDR3_Memory_controller_RegistersVal.dat

emif4Cfg upload from 0x008ffd20

emif4Cfg_0x008ffd20_C.dat

emif4Cfg file

/* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include "tiboot.h"
#include "platform.h"

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
	BOOT_EMIF_ENABLE_SLSW_config6 | \
	BOOT_EMIF_ENABLE_SLSW_config7 | \
	BOOT_EMIF_ENABLE_SLSW_config8 | \
	BOOT_EMIF_ENABLE_SLSW_config9 | \
	BOOT_EMIF_ENABLE_SLSW_config10 | \
	BOOT_EMIF_ENABLE_SLSW_config18 | \
	BOOT_EMIF_ENABLE_SLSW_config19 | \
	BOOT_EMIF_ENABLE_SLSW_config20 | \
	BOOT_EMIF_ENABLE_SLSW_config22 | \
	BOOT_EMIF_ENABLE_SLSW_config12 | \
	BOOT_EMIF_ENABLE_SLSW_config23 | \
	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
    
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */

    0x63066A32,/*0x62477AB2,  *//* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x00001457,/*0x0000144F,  *//* sdRamRefreshCtl  */
    0x1113783C,/*0x1333780C,  *//* sdRamTiming1 */
    0x30B37FE3,/*0x30717FE3,  *//* sdRamTiming2 */
    0x559F8ADF,/*0x559F86AF,  *//* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074C1F,/*0x70074c1f,  *//* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x020021EF,/*0x0010010F,  *//* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    /*0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,*/

    /*0         1  2  3  4  5  6     7*/
    0x87A0007F, 0, 0, 0, 0, 0, 0x54, 0x56,
    /*8   9     10    11 12          13 14 15*/
    0x6D, 0x69, 0x00, 0, 0x0AF0000F, 0, 0, 0,
  /*16 17 18    19    20    21    22    23*/
    0, 0, 0xAA, 0xA9, 0xAF, 0xB4, 0x00, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
    
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};
	
#define GPIO_BASE (0x2320000)
#define GPIO_DIR_OFFSET (0x10)
#define GPIO_SETDATA_OFFSET (0x18)
#define GPIO_CLEARDATA_OFFSET (0x1C)

void testfunc();

void testfunc()
{

    while (1)
    {
        asm("   IDLE");

    }
}

void main(void)
{

    volatile uint32_t *reg_val;

     reg_val = (volatile uint32_t *)(GPIO_BASE + GPIO_DIR_OFFSET);
     // configure as output pin -- write 0 to the Direction register
     *reg_val &= ~ (1 << 8);


     reg_val = (volatile uint32_t *) (GPIO_BASE + GPIO_SETDATA_OFFSET);
     // Write value 1 in the set data register, so that Out data register will be 1
     *reg_val |= (1 << 8);
    testfunc();


}
	

If you could use your valuable time to help me analyze where emif4Cfg is not configured correctly, I would greatly appreciate itBootConfiguration.zip

Dear Customer,

Let me try to derive some steps for you to debug the emif4cfg with respect to the direct boot example.

And then, you may try to do some similar steps for SRIo boot too.

Give me a day or two.

Let me get back.

Regards

Shankari G

Hi Shankari G

I read sprugy5c againg. In section 2.2.1 Initialization Process After Power On Reset

I see the word:

The RBL also provides an ability for the user to configure the DDR EMIF before loading the image into the external memory during the boot process using a DDR structure. This structure is reserved in the L2. For every section that the RBL reads, it verifies if the DDR enable magic word is set. If the magic word is set, then the DDR structure is used to initialize the DDR. The structure definition of the DDR varies from device to device. See the device-specific data manual for the DDR configuration structure.

I guess maybe i didn't set the DDR enable magic. Do you know what address is DDR enable magic word?

Dear Customer,

In the spiboot.c of the direct boot example, 

This is the emif4cfg data table required for booting.

======================================

Please compare it with yours.

#pragma DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T emif4Cfg = {

BOOT_EMIF4_ENABLE_MSW_pllCtl | \
BOOT_EMIF4_ENABLE_MSW_sdRamTiming1 | \
BOOT_EMIF4_ENABLE_MSW_sdRamTiming2 | \
BOOT_EMIF4_ENABLE_MSW_sdRamTiming3 | \
BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1 | \
BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

BOOT_EMIF_ENABLE_SLSW_config0 | \
BOOT_EMIF_ENABLE_SLSW_config6 | \
BOOT_EMIF_ENABLE_SLSW_config7 | \
BOOT_EMIF_ENABLE_SLSW_config8 | \
BOOT_EMIF_ENABLE_SLSW_config9 | \
BOOT_EMIF_ENABLE_SLSW_config10 | \
BOOT_EMIF_ENABLE_SLSW_config18 | \
BOOT_EMIF_ENABLE_SLSW_config19 | \
BOOT_EMIF_ENABLE_SLSW_config20 | \
BOOT_EMIF_ENABLE_SLSW_config22 | \
BOOT_EMIF_ENABLE_SLSW_config12 | \
BOOT_EMIF_ENABLE_SLSW_config23 | \
BOOT_EMIF_ENABLE_SLSW_config21, /* Config select slsw */
0, /* Config select lsw */

3, /* pllPrediv */
40, /* pllMult */
2, /* pllPostDiv */

0x62477AB2, /* sdRamConfig */
0, /* sdRamConfig2, dont care*/
0x0000144F, /* sdRamRefreshCtl */
0x1333780C, /* sdRamTiming1 */
0x30717FE3, /* sdRamTiming2 */
0x559F86AF, /* sdRamTiming3 */

0, /* lpDdrNvmTiming, dont care */
0, /* powerManageCtl, dont care */
0, /* iODFTTestLogic, dont care */
0, /* performCountCfg, dont care */
0, /* performCountMstRegSel, dont care */
0, /* readIdleCtl, dont care */
0, /* sysVbusmIntEnSet, dont care */
0x70074c1f, /* sdRamOutImpdedCalCfg, dont care */
0, /* tempAlterCfg, dont care */

0x0010010F, /* ddrPhyCtl1 */

0, /* ddrPhyCtl2, dont care */
0, /* priClassSvceMap, dont care */
0, /* mstId2ClsSvce1Map, dont care */
0, /* mstId2ClsSvce2Map, dont care */
0, /* eccCtl, dont care */
0, /* eccRange1, dont care */
0, /* eccRange2, dont care */
0, /* rdWrtExcThresh, dont care */

0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
};

0636.C6657_directROM_Boot_example.zip

Regards

Shankari G