AM62A7: Ethernet Port Connections - Clarification

Part Number: AM62A7

Tool/software:

Hello TI Team,

I am referring TRM for TDA4V Mid Eco and AM62A7 MCUs concurrently and I was evaluating the Isolation techniques for Ethernet Ports.

For TDA4 series, the 2 Ethernet ports are physically isolated from each other -- one connected to Main Domain and the other connected to the MCU Island.

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On the other side, AM62x MCU has a different approach:

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I want to know if they are physically isolated? What cores are they connected to internally? Can they be configured separately -- one to ARM Cortex A53x Application Cores and the other to MCU Island ARM Cortex R5F? Also as I understand, MCU Island with ARM Cortex R5F is FFI Isolated from other cores which is an added advantage for the topic I am working on. Correct me if I am wrong and if you could also give me some additional pointers on how they are Isolated to as to go further for Cybersecurity perspective, it would help me.

Thank you for your time.  

  • Attaching the images again in case it got missed in the post: 

  • Hello Srikar,

    Can they be configured separately -- one to ARM Cortex A53x Application Cores and the other to MCU Island ARM Cortex R5F?

    Can you describe specifically what use case you are looking to do with this?

    Is there a particular reason for targeting AM62x (in your inquiry) or AM62Ax (listed in the title of your inquiry)?

    -Daolin

  • There are certain functions which are being implemented in both the cores and from Cybersecurity perspective, I am trying to ensure Security Goals as a part of Isolation techniques [Functional, Physical and Logical (if applicable)]. That being said, the 2 ethernet ports will be responsible for different functionalities and the data from both the ports should be STRICTLY isolated thus protecting in case of the ECU compromise.

    For our current analysis, we are trying to evaluate TDA4 and AM62x MCUs and trying to define Security Isolation concepts as a part of Domain Controllers.

  • Hi Srikar, 

    As a short answer to your question, on AM62x devices the CPSW peripheral is that is only on the Main domain, the two CPSW ports are not physically isolated from each other. 

    Furthermore, if you have going to put firewall between your Main and MCU domains, it is not possible to split one CPSW ethernet port on A53 and the other port on R5F.

    That being said, if your purpose is to have 2 ethernet ports that are isolated from each other, have you considered the AM64x processors which feature CPSW ethernet and PRU_ICSSG ethernet ports? This could enable you to set up CPSW ethernet on A53 and PRU_ICSSG on the R5F cores (or vice versa).

    -Daolin

  • I want to share a screenshot based on the analysis of AM62x Security Overview which is TI Confidential NDA. Not sure if this is the right platform to share the screenshot. If it is fine, I can share here.   

  • Hi Srikar,

    This is a public e2e forum so you should not share the screenshot here.

    Do you have a field apps engineer working directly with you? I assume you have or have been working with a TI representative because of this NDA content. Perhaps you can email the FAE and me (you can find my email from my E2E profile). 

    -Daolin

  • Is this what you meant to reach out to you? Slight smile

  • Hi Srikar,

    Yes, that is also an option to reach out to me through an e2e private message. 

    -Daolin