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[FAQ] AM625 / AM623 / AM620-Q1 / AM62Ax / AM62Px / AM62D-Q1 / AM62L / AM64x / AM243x Design Recommendations / Custom board hardware design - Drive Strength Configuration for SDIO and LVCMOS I/Os

Kallikuppa Sreenivasa
Guru**** 191119 points
Part Number: AM625
Other Parts Discussed in Thread: AM62A7,

Tool/software:

Hi TI Experts,

I have the below query

AM62A7: How can we change the drive strength of the SPI interface
AM625: How to change the drive strength of the ethernet interface IOs
AM625: How to change the drive strength of the OSPI interface IOs

In general can i configure the drive strength for the SOC IOs or peripherals.

  • 0
    TI__Guru**** 191119 points

    Hi Board designers, 


    We do not currently support changing the drive strength.

    We only support the default drive strength currently, and customer should use the device IBIS models to understand the actual output buffer drive strength.

     Drive Strength Configuration:

    TI currently does not support configuring any other drive strength besides the nominal (default) value for SDIO and LVCMOS buffers, as the nominal value is the only configuration at which chip-level STA (Static Timing Analysis) is closed. The nominal value corresponds to a 40Ω for SDIO and 60Ω for LVCMOS. The IBIS model has been updated to contain only drive strengths where the timing is closed internally.

    The drive strength must remain in the default state since this is the only condition used during timing closure of the peripherals.

    The SOC has been currently configured for proper operation when using the default drive strength.
    Changing the drive strength may cause functional issues. Therefore, we currently do not support changing drive strengths.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 191119 points

    Hi TI Experts,

    Do you have plans to support other drive strengths other than the default drive strength?

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 191119 points

    Hi Board designers, 

    We do not currently support changing the drive strength.

    We have received similar requests. The Systems/Design team is reviewing, analyzing the requests and performing internal simulations.

    We are internally performing simulation and tests to support drive strength configuration for the LVCMOS IO.

    We are planning to support NOM (currently configured) and FAST drive strength.

    I have no additional inputs or timeline for inputs. I will update the FAQ when i hear from the team.

    Last Updated: 30th August 2025

    Regards,

    Sreenivasa

     

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 191119 points

    Hi Board designers, 

    Additional inputs:

    (43) AM625 / AM623 / AM62A / AM62P / AM62D-Q1 / AM64x / AM243x hardware design - I/O Drive Strength Configuration for SDIO and LVCMOS - Processors forum - Processors - TI E2E support forums

    • the PCB track must be 40 Ohm to match the driver/receiver impedances of SDIO MMC1 (CLK + DAT0-3 + CMD)

     Customer needs to consider the impact of trace impedance on their entire system implementation.  This not something TI can answer.  For example: 40 ohms may be a better match for the AM64X output impedance, but it may not be the best match for the attached device.  In reality, it may be better to split the difference and target a trace impedance of 45 ohms if the attached device has a 50 ohm source impedance.  This is why customer should be performing simulations to validate signal quality on their specific system implementation.

    Slew rate control and source impedance are two different things.  We do not provide slew rate control on the IOs implemented in AM64x.  The device is trimmed during final test to target a fixed source impedance as defined in the IBIS model.  All peripherals were timing is closed based on the source impedance defined in the IBIS model.  This should be 40 ohms for the IOs associated with MMC1

    Regards,

    Sreenivasa