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AM6421: AM6421 : Can PRU_ICSSG0 RGMII2/RGMII1 be enabled in Linux with a single instance.

Nikhil Jarande
Intellectual 390 points
Part Number: AM6421
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

We are designing a custom board with the following components:

Processor: AM6421
PHY: DP83822
Configuration:
A) Two Ethernet ports for industrial protocols using MII connection with R5F running FreeRTOS.
B) One Ethernet port for OPC UA using RMII/RGMII connection with A53 running Linux.

Constraints:
When using PRU_ICSSG1 for EtherCAT (example use case), the CPSW block with RMII connection cannot be used for the OPC UA port due to pin conflicts:

IOSET1: CRS and COL pins conflict.
IOSET2: MDIO pin conflict.
The only feasible option for OPC UA is using PRU_ICSSG0 with RGMII.

Query:
Can PRU_ICSSG0 RGMII2/RGMII1 be enabled in Linux with a single instance?
Any references or guidance on enabling and configuring this setup in Linux would be highly appreciated.

  • +1
    TI__Guru* 89115 points

    Hello Nikhil,

    Yes, we do support using only one of the 2 possible PRU Ethernet ports in an ICSSG instance. That is actually the default behavior of the AM64x EVM, so you can refer to this file for a template of how we enable only a single PRU Ethernet port:
    ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-am642-evm.dts

    The Linux SDK docs says that an unused port should be enabled and marked as "fixed-link" in the Linux devicetree file. However, I think that is wrong, as our example devicetree file above clearly disables the unused port. I have filed a bug report against that line in the Linux SDK docs: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/10_00_07_04/exports/docs/linux/Foundational_Components/PRU-ICSS/Linux_Drivers/PRU_ICSSG_Ethernet.html

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 390 points

    Thanks for quick response 

    A) ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-am642-evm.dts : Not able to navigate Link.

    B) Is it possible to use CPSW port without MDIO in Linux for OPCUA ? Considering configuration done by register strapping register.

  • 0 in reply to Nikhil Jarande
    TI__Guru* 89115 points

    Hello Nikhil,

    We support the AM64x Linux SDK on these forums. In your Linux SDK download, you can find the Linux code under board-support/ti-linux-kernel-x.x.x folder.

    I am reassigning your thread to another team member to comment on the CPSW question.

    Regards,

    Nick

  • +1 in reply to Nikhil Jarande
    TI__Expert 8825 points

    Hi Nikhil,

    Nikhil Jarande said:
    B) Is it possible to use CPSW port without MDIO in Linux for OPCUA ? Considering configuration done by register strapping register.

    May I ask why you are looking to use the CPSW port without MDIO? In general for Linux, during the boot up process the MDIO is necessary to detect the PHY and attach the relevant PHY driver. 

    From my understanding, usually when a MAC-to-MAC connection is needed, then MDIO is not necessary, and the "fixed-link" property must be enabled in the Linux device tree.

    -Daolin

  • 0 in reply to Daolin Qiu
    Intellectual 390 points

    Hi Daolin,

    When using PRU_ICSSG1 for EtherCAT (example use case), the CPSW block with RMII connection cannot be used for the OPC UA port due to pin conflicts:

    IOSET1: CRS and COL pins conflict.
    IOSET2: MDIO pin conflict.

    I thought if we can use IOSET2 in CPSW by compromise MDIO pins and configuration can done through Register strapping. 

    Thanks,

    Nikhil

  • 0 in reply to Nick Saulnier
    Intellectual 390 points

    Thanks Nick for Reply.

  • 0 in reply to Nikhil Jarande
    Intellectual 390 points

     , : Apologies coming back to same thread as it is having context.  Is it possible to use CPSW with different MDIO set in Linux with RMII interface ? MDIO set information : PRG1_MDIO0_MDIO , PRG1_MDIO0_MDC.  In MCU_PLUS_SDK , its not possible as Sysconfig restricts it.

  • 0 in reply to Nikhil Jarande
    TI__Expert 8825 points

    Hi Nikhil,

    Nikhil Jarande said:
    Is it possible to use CPSW with different MDIO set in Linux with RMII interface ? MDIO set information : PRG1_MDIO0_MDIO , PRG1_MDIO0_MDC.  In MCU_PLUS_SDK , its not possible as Sysconfig restricts it.

    I believe the Sysconfig restricts it because as you mentioned, there would be a pinmux conflict. 

    Nikhil Jarande said:
    IOSET1: CRS and COL pins conflict.
    IOSET2: MDIO pin conflict.

    Can you explain specifically which pins are conflicting (including the pin number and pin name) with MDIO for CPSW? Can you share a copy of device tree (including your current pinmux configurations causing the conflicts)?

    Nikhil Jarande said:
    Constraints:
    When using PRU_ICSSG1 for EtherCAT (example use case), the CPSW block with RMII connection cannot be used for the OPC UA port due to pin conflicts:
    Nikhil Jarande said:
    The only feasible option for OPC UA is using PRU_ICSSG0 with RGMII.

    Is there a particular reason for needing to use PRU_ICSSG1 with CPSW or is PRU_ICSSG0 with CPSW sufficient?

    -Daolin

  • 0 in reply to Daolin Qiu
    Intellectual 390 points

    Hi Daolin,

    Thanks for Reply.

    Processor: AM6421
    PHY: DP83822

    Requirement

    • Two Ethernet ports for industrial protocols using MII connection with R5F running FreeRTOS.
    •  One Ethernet port for OPC UA using RMII/RGMII connection with A53 running Linux.

    Current configuration and Constraint

    • Industrial Port (MII) -> PRU_ICSSG1 -> ( syscfg is same as per example given in SDK for Ethercat , also attached at bottom)
    • OPCUA Port (RMII) -> CPSW

             Pin conflict information of CPSW RMII port with PRU_ICSSG1 with two MII ports in glance

    Alternative Options

    We would prefer not to switch PRU_ICSSG1 to PRU_ICSSG0 for the industrial protocol, as one revision of hardware and EVM is already working with PRU_ICSSG1.

    Option 1:

    • Industrial Port (MII): PRU_ICSSG1
    • OPCUA Port (RMII): CPSW -> IOSET2 but different MDIO Ports : PRG0_MDIO0_MDC , PRG0_MDIO0_MDIO

    Option 2:

    • Industrial Port (MII): PRU_ICSSG1
    • OPCUA Port (RGMII): PRU_ICSSG0

    Query:

    Is Option 1 achievable for CPSW in Linux?If yes, could you provide any relevant documentation or guidance? If not, we need to proceed with Option 2.We look forward to your input on this matter.

    Syscfg

    8561.Ethercat_syscfg.txt 
    /**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM64x" --package "ALV" --part "Default" --context "r5fss0-0" --product "INDUSTRIAL_COMMUNICATIONS_SDK_AM64X@09.02.00"
 * @versions {"tool":"1.20.0+3587"}
 */

/**
 * Import the modules used in this configuration.
 */
const eeprom          = scripting.addModule("/board/eeprom/eeprom", {}, false);
const eeprom1         = eeprom.addInstance();
const flash           = scripting.addModule("/board/flash/flash", {}, false);
const flash1          = flash.addInstance();
const led             = scripting.addModule("/board/led/led", {}, false);
const led1            = led.addInstance();
const led2            = led.addInstance();
const led3            = led.addInstance();
const gpio            = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1           = gpio.addInstance();
const i2c             = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1            = i2c.addInstance();
const i2c2            = i2c.addInstance();
const pruicss         = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1        = pruicss.addInstance();
const ethercat        = scripting.addModule("/industrial_comms/ethercat/ethercat", {}, false);
const ethercat1       = ethercat.addInstance();
const debug_log       = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7       = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71      = mpu_armv7.addInstance();
const mpu_armv72      = mpu_armv7.addInstance();
const mpu_armv73      = mpu_armv7.addInstance();
const mpu_armv74      = mpu_armv7.addInstance();
const mpu_armv75      = mpu_armv7.addInstance();
const default_linker  = scripting.addModule("/memory_configurator/default_linker", {}, false);
const default_linker1 = default_linker.addInstance();
const general         = scripting.addModule("/memory_configurator/general", {}, false);
const general1        = general.addInstance();
const region          = scripting.addModule("/memory_configurator/region", {}, false);
const region1         = region.addInstance();
const section         = scripting.addModule("/memory_configurator/section", {}, false);
const section1        = section.addInstance();
const section2        = section.addInstance();
const section3        = section.addInstance();
const section4        = section.addInstance();
const section5        = section.addInstance();
const section6        = section.addInstance();
const section7        = section.addInstance();
const section8        = section.addInstance();
const section9        = section.addInstance();
const section10       = section.addInstance();
const section11       = section.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
eeprom1.$name = "CONFIG_EEPROM0";

flash1.$name                  = "CONFIG_FLASH0";
flash1.peripheralDriver.$name = "CONFIG_OSPI0";

led1.name  = "TPIC2810";
led1.$name = "CONFIG_LED_DIGITAL_OUTPUT";

led2.$name = "CONFIG_LED_RUN";

led3.name    = "Ioexp";
led3.ioIndex = 16;
led3.$name   = "CONFIG_LED_ERROR";

gpio1.$name                    = "CONFIG_GPIO0";
led2.peripheralDriver          = gpio1;
gpio1.pinDir                   = "OUTPUT";
gpio1.useMcuDomainPeripherals  = true;
gpio1.MCU_GPIO.$assign         = "MCU_GPIO0";
gpio1.MCU_GPIO.gpioPin.$assign = "MCU_SPI1_CS0";

i2c1.$name               = "CONFIG_I2C0";
eeprom1.peripheralDriver = i2c1;
i2c1.I2C.$assign         = "I2C0";
i2c1.I2C.SCL.$assign     = "I2C0_SCL";
i2c1.I2C.SDA.$assign     = "I2C0_SDA";
i2c1.I2C_child.$name     = "drivers_i2c_v0_i2c_v0_template1";

i2c2.$name            = "CONFIG_I2C1";
led1.peripheralDriver = i2c2;
led3.peripheralDriver = i2c2;
i2c2.I2C.$assign      = "I2C1";
i2c2.I2C.SCL.$assign  = "I2C1_SCL";
i2c2.I2C.SDA.$assign  = "I2C1_SDA";
i2c2.I2C_child.$name  = "drivers_i2c_v0_i2c_v0_template2";

ethercat1.$name              = "CONFIG_ETHERCAT0";
ethercat1.instance           = "ICSSG1";
ethercat1.ethphy[0].$name    = "CONFIG_ETHPHY0";
ethercat1.ethphy[1].$name    = "CONFIG_ETHPHY1";
ethercat1.ethphy[1].mdioPort = 3;

pruicss1.iepSyncMode                     = scripting.forceWrite(true);
ethercat1.icss                           = pruicss1;
pruicss1.$name                           = "CONFIG_PRU_ICSS1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";

debug_log.enableUartLog = true;
debug_log.enableCssLog  = false;
debug_log.uartLog.$name = "CONFIG_UART0";

const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
const uart_v0_template1 = uart_v0_template.addInstance({}, false);
uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
debug_log.uartLog.child = uart_v0_template1;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;

mpu_armv75.$name    = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr = 0x80000000;
mpu_armv75.size     = 31;

default_linker1.$name = "memory_configurator_default_linker0";

general1.$name        = "CONFIG_GENERAL0";
general1.stack_size   = 32768;
general1.linker.$name = "TIARMCLANG0";

region1.$name                               = "MEMORY_REGION_CONFIGURATION0";
region1.memory_region.create(9);
region1.memory_region[0].type               = "TCMA_R5F";
region1.memory_region[0].$name              = "R5F_VECS";
region1.memory_region[0].size               = 0x40;
region1.memory_region[0].auto               = false;
region1.memory_region[1].type               = "TCMA_R5F";
region1.memory_region[1].$name              = "R5F_TCMA";
region1.memory_region[1].size               = 0x7FC0;
region1.memory_region[2].type               = "TCMB_R5F";
region1.memory_region[2].$name              = "R5F_TCMB0";
region1.memory_region[2].size               = 0x8000;
region1.memory_region[3].$name              = "NON_CACHE_MEM";
region1.memory_region[3].auto               = false;
region1.memory_region[3].manualStartAddress = 0x70060000;
region1.memory_region[3].size               = 0x8000;
region1.memory_region[4].$name              = "MSRAM";
region1.memory_region[4].auto               = false;
region1.memory_region[4].manualStartAddress = 0x70080000;
region1.memory_region[4].size               = 0x80000;
region1.memory_region[5].type               = "FLASH";
region1.memory_region[5].$name              = "FLASH";
region1.memory_region[5].auto               = false;
region1.memory_region[5].manualStartAddress = 0x60100000;
region1.memory_region[5].size               = 0x80000;
region1.memory_region[6].$name              = "USER_SHM_MEM";
region1.memory_region[6].auto               = false;
region1.memory_region[6].manualStartAddress = 0x701D0000;
region1.memory_region[6].size               = 0x80;
region1.memory_region[6].isShared           = true;
region1.memory_region[6].shared_cores       = ["a53ss0-0","a53ss0-1","m4fss0-0","r5fss0-1","r5fss1-1"];
region1.memory_region[7].auto               = false;
region1.memory_region[7].manualStartAddress = 0x701D0080;
region1.memory_region[7].size               = 0x3F80;
region1.memory_region[7].$name              = "LOG_SHM_MEM";
region1.memory_region[7].isShared           = true;
region1.memory_region[7].shared_cores       = ["a53ss0-0","a53ss0-1","m4fss0-0","r5fss0-1","r5fss1-1"];
region1.memory_region[8].auto               = false;
region1.memory_region[8].manualStartAddress = 0x701D4000;
region1.memory_region[8].size               = 0xC000;
region1.memory_region[8].$name              = "RTOS_NORTOS_IPC_SHM_MEM";
region1.memory_region[8].isShared           = true;
region1.memory_region[8].shared_cores       = ["a53ss0-0","a53ss0-1","m4fss0-0","r5fss0-1","r5fss1-1"];

section1.$name                        = "Vector Table";
section1.load_memory                  = "R5F_VECS";
section1.group                        = false;
section1.output_section.create(1);
section1.output_section[0].$name      = ".vectors";
section1.output_section[0].palignment = true;

section2.$name                        = "Text Segments";
section2.load_memory                  = "MSRAM";
section2.output_section.create(5);
section2.output_section[0].$name      = ".text.hwi";
section2.output_section[0].palignment = true;
section2.output_section[1].$name      = ".text.cache";
section2.output_section[1].palignment = true;
section2.output_section[2].$name      = ".text.mpu";
section2.output_section[2].palignment = true;
section2.output_section[3].$name      = ".text.boot";
section2.output_section[3].palignment = true;
section2.output_section[4].$name      = ".text:abort";
section2.output_section[4].palignment = true;

section3.$name                        = "Code and Read-Only Data";
section3.load_memory                  = "MSRAM";
section3.output_section.create(2);
section3.output_section[0].$name      = ".text";
section3.output_section[0].palignment = true;
section3.output_section[1].$name      = ".rodata";
section3.output_section[1].palignment = true;

section4.$name                        = "Data Segment";
section4.load_memory                  = "MSRAM";
section4.output_section.create(1);
section4.output_section[0].$name      = ".data";
section4.output_section[0].palignment = true;

section5.$name                                   = "Memory Segments";
section5.load_memory                             = "MSRAM";
section5.output_section.create(3);
section5.output_section[0].$name                 = ".bss";
section5.output_section[0].palignment            = true;
section5.output_section[0].output_sections_start = "__BSS_START";
section5.output_section[0].output_sections_end   = "__BSS_END";
section5.output_section[1].$name                 = ".sysmem";
section5.output_section[1].palignment            = true;
section5.output_section[2].$name                 = ".stack";
section5.output_section[2].palignment            = true;

section6.$name                                    = "Stack Segments";
section6.load_memory                              = "MSRAM";
section6.output_section.create(5);
section6.output_section[0].$name                  = ".irqstack";
section6.output_section[0].output_sections_start  = "__IRQ_STACK_START";
section6.output_section[0].output_sections_end    = "__IRQ_STACK_END";
section6.output_section[0].input_section.create(1);
section6.output_section[0].input_section[0].$name = ". = . + __IRQ_STACK_SIZE;";
section6.output_section[1].$name                  = ".fiqstack";
section6.output_section[1].output_sections_start  = "__FIQ_STACK_START";
section6.output_section[1].output_sections_end    = "__FIQ_STACK_END";
section6.output_section[1].input_section.create(1);
section6.output_section[1].input_section[0].$name = ". = . + __FIQ_STACK_SIZE;";
section6.output_section[2].$name                  = ".svcstack";
section6.output_section[2].output_sections_start  = "__SVC_STACK_START";
section6.output_section[2].output_sections_end    = "__SVC_STACK_END";
section6.output_section[2].input_section.create(1);
section6.output_section[2].input_section[0].$name = ". = . + __SVC_STACK_SIZE;";
section6.output_section[3].$name                  = ".abortstack";
section6.output_section[3].output_sections_start  = "__ABORT_STACK_START";
section6.output_section[3].output_sections_end    = "__ABORT_STACK_END";
section6.output_section[3].input_section.create(1);
section6.output_section[3].input_section[0].$name = ". = . + __ABORT_STACK_SIZE;";
section6.output_section[4].$name                  = ".undefinedstack";
section6.output_section[4].output_sections_start  = "__UNDEFINED_STACK_START";
section6.output_section[4].output_sections_end    = "__UNDEFINED_STACK_END";
section6.output_section[4].input_section.create(1);
section6.output_section[4].input_section[0].$name = ". = . + __UNDEFINED_STACK_SIZE;";

section7.$name                        = "Initialization and Exception Handling";
section7.load_memory                  = "MSRAM";
section7.output_section.create(3);
section7.output_section[0].$name      = ".ARM.exidx";
section7.output_section[0].palignment = true;
section7.output_section[1].$name      = ".init_array";
section7.output_section[1].palignment = true;
section7.output_section[2].$name      = ".fini_array";
section7.output_section[2].palignment = true;

section8.$name                       = "User Shared Memory";
section8.type                        = "NOLOAD";
section8.load_memory                 = "USER_SHM_MEM";
section8.group                       = false;
section8.output_section.create(1);
section8.output_section[0].$name     = ".bss.user_shared_mem";
section8.output_section[0].alignment = 0;

section9.$name                       = "Log Shared Memory";
section9.load_memory                 = "LOG_SHM_MEM";
section9.type                        = "NOLOAD";
section9.group                       = false;
section9.output_section.create(1);
section9.output_section[0].$name     = ".bss.log_shared_mem";
section9.output_section[0].alignment = 0;

section10.$name                       = "IPC Shared Memory";
section10.type                        = "NOLOAD";
section10.load_memory                 = "RTOS_NORTOS_IPC_SHM_MEM";
section10.group                       = false;
section10.output_section.create(1);
section10.output_section[0].$name     = ".bss.ipc_vring_mem";
section10.output_section[0].alignment = 0;

section11.$name                       = "Non Cacheable Memory";
section11.load_memory                 = "NON_CACHE_MEM";
section11.group                       = false;
section11.type                        = "NOLOAD";
section11.output_section.create(1);
section11.output_section[0].$name     = ".bss.nocache";
section11.output_section[0].alignment = 0;

/**
 * These are the reserved peripherals and settings in this configuration
 */
const iPRU_ICSSG0_IEP1 = scripting.addPeripheral("PRU_ICSSG0_IEP");
iPRU_ICSSG0_IEP1.$name = "MyPRU_ICSSG0_IEP1";

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
flash1.peripheralDriver.OSPI.$suggestSolution                = "OSPI0";
flash1.peripheralDriver.OSPI.CLK.$suggestSolution            = "OSPI0_CLK";
flash1.peripheralDriver.OSPI.CSn0.$suggestSolution           = "OSPI0_CSn0";
flash1.peripheralDriver.OSPI.DQS.$suggestSolution            = "OSPI0_DQS";
flash1.peripheralDriver.OSPI.D7.$suggestSolution             = "OSPI0_D7";
flash1.peripheralDriver.OSPI.D6.$suggestSolution             = "OSPI0_D6";
flash1.peripheralDriver.OSPI.D5.$suggestSolution             = "OSPI0_D5";
flash1.peripheralDriver.OSPI.D4.$suggestSolution             = "OSPI0_D4";
flash1.peripheralDriver.OSPI.D3.$suggestSolution             = "OSPI0_D3";
flash1.peripheralDriver.OSPI.D2.$suggestSolution             = "OSPI0_D2";
flash1.peripheralDriver.OSPI.D1.$suggestSolution             = "OSPI0_D1";
flash1.peripheralDriver.OSPI.D0.$suggestSolution             = "OSPI0_D0";
ethercat1.PRU_ICSSG1_MDIO.$suggestSolution                   = "PRU_ICSSG1_MDIO0";
ethercat1.PRU_ICSSG1_MDIO.MDC.$suggestSolution               = "PRG1_MDIO0_MDC";
ethercat1.PRU_ICSSG1_MDIO.MDIO.$suggestSolution              = "PRG1_MDIO0_MDIO";
ethercat1.PRU_ICSSG1_IEP.$suggestSolution                    = "PRU_ICSSG1_IEP0";
ethercat1.PRU_ICSSG1_IEP.EDC_LATCH_IN0.$suggestSolution      = "PRG1_PRU0_GPO18";
ethercat1.PRU_ICSSG1_IEP.EDC_LATCH_IN1.$suggestSolution      = "PRG1_PRU0_GPO7";
ethercat1.PRU_ICSSG1_IEP.EDC_SYNC_OUT0.$suggestSolution      = "PRG1_PRU0_GPO19";
ethercat1.PRU_ICSSG1_IEP.EDC_SYNC_OUT1.$suggestSolution      = "PRG1_PRU0_GPO17";
ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT28.$suggestSolution = "PRG1_PRU0_GPO9";
ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT29.$suggestSolution = "PRG1_PRU0_GPO10";
ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT30.$suggestSolution = "PRG1_PRU1_GPO9";
ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT31.$suggestSolution = "PRG1_PRU1_GPO10";
ethercat1.PRU_ICSSG1_MII_G_RT.$suggestSolution               = "PRU_ICSSG1_MII_G_RT";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXD0.$suggestSolution     = "PRG1_PRU0_GPO0";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXD1.$suggestSolution     = "PRG1_PRU0_GPO1";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXD2.$suggestSolution     = "PRG1_PRU0_GPO2";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXD3.$suggestSolution     = "PRG1_PRU0_GPO3";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXDV.$suggestSolution     = "PRG1_PRU0_GPO4";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXER.$suggestSolution     = "PRG1_PRU0_GPO5";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_RXLINK.$suggestSolution   = "PRG1_PRU0_GPO8";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_TXD0.$suggestSolution     = "PRG1_PRU0_GPO11";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_TXD1.$suggestSolution     = "PRG1_PRU0_GPO12";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_TXD2.$suggestSolution     = "PRG1_PRU0_GPO13";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_TXD3.$suggestSolution     = "PRG1_PRU0_GPO14";
ethercat1.PRU_ICSSG1_MII_G_RT.MII0_TXEN.$suggestSolution     = "PRG1_PRU0_GPO15";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXD0.$suggestSolution     = "PRG1_PRU1_GPO0";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXD1.$suggestSolution     = "PRG1_PRU1_GPO1";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXD2.$suggestSolution     = "PRG1_PRU1_GPO2";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXD3.$suggestSolution     = "PRG1_PRU1_GPO3";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXDV.$suggestSolution     = "PRG1_PRU1_GPO4";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXER.$suggestSolution     = "PRG1_PRU1_GPO5";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_RXLINK.$suggestSolution   = "PRG1_PRU1_GPO8";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_TXD0.$suggestSolution     = "PRG1_PRU1_GPO11";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_TXD1.$suggestSolution     = "PRG1_PRU1_GPO12";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_TXD2.$suggestSolution     = "PRG1_PRU1_GPO13";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_TXD3.$suggestSolution     = "PRG1_PRU1_GPO14";
ethercat1.PRU_ICSSG1_MII_G_RT.MII1_TXEN.$suggestSolution     = "PRG1_PRU1_GPO15";
ethercat1.PRU_ICSSG1_MII_G_RT.MII_MR0_CLK.$suggestSolution   = "PRG1_PRU0_GPO6";
ethercat1.PRU_ICSSG1_MII_G_RT.MII_MR1_CLK.$suggestSolution   = "PRG1_PRU1_GPO6";
ethercat1.PRU_ICSSG1_MII_G_RT.MII_MT0_CLK.$suggestSolution   = "PRG1_PRU0_GPO16";
ethercat1.PRU_ICSSG1_MII_G_RT.MII_MT1_CLK.$suggestSolution   = "PRG1_PRU1_GPO16";
debug_log.uartLog.UART.$suggestSolution                      = "USART0";
debug_log.uartLog.UART.RXD.$suggestSolution                  = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution                  = "UART0_TXD";
iPRU_ICSSG0_IEP1.$suggestSolution                            = "PRU_ICSSG0_IEP0";
iPRU_ICSSG0_IEP1.EDC_LATCH_IN0.$suggestSolution              = "PRG0_PRU0_GPO18";
iPRU_ICSSG0_IEP1.EDC_LATCH_IN1.$suggestSolution              = "PRG0_PRU0_GPO7";
iPRU_ICSSG0_IEP1.EDC_SYNC_OUT0.$suggestSolution              = "PRG0_PRU0_GPO19";
iPRU_ICSSG0_IEP1.EDC_SYNC_OUT1.$suggestSolution              = "PRG0_PRU0_GPO17";
iPRU_ICSSG0_IEP1.EDIO_DATA_IN_OUT28.$suggestSolution         = "PRG0_PRU0_GPO9";
iPRU_ICSSG0_IEP1.EDIO_DATA_IN_OUT29.$suggestSolution         = "PRG0_PRU0_GPO10";
iPRU_ICSSG0_IEP1.EDIO_DATA_IN_OUT30.$suggestSolution         = "PRG0_PRU1_GPO9";
iPRU_ICSSG0_IEP1.EDIO_DATA_IN_OUT31.$suggestSolution         = "PRG0_PRU1_GPO10";
iPRU_ICSSG0_IEP1.EDIO_OUTVALID.$suggestSolution              = "SPI0_CS1";

  • 0 in reply to Nikhil Jarande
    TI__Expert 8825 points

    Hi Nikhil,

    For COL and CRS Pin Conflict:

    I took a closer look into your attached syscfg and noticed that the below pins of the CPSW interface which you stated had a conflict with CRS and COL of the ICSSG interfaces appears to be assigned to a completely different set of signals of the ICSSG interfaces? They seem to be assigned to PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT signals in your sysconfig. In fact, the CRS and COL signals don't seem to be assigned at all in your attached sysconfig?

    CPSW pins that you shared were conflicting with CRS and COL of the ICSSG interfaces:

    Ball Name CPSW Signal ICSSG Signal
    PRG1_PRU0_GPO9  RMII_REF_CLK PR1_MII0_COL
    PRG1_PRU0_GPO10  RMII1_RX_ER PR1_MII0_CRS
    PRG1_PRU1_GPO9  RMII1_RXD1 PR1_MII1_COL
    PRG1_PRU1_GPO10  RMII1_TXD0 PR1_MII1_CRS

    Your attached sysconfig:

    ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT28.$suggestSolution = "PRG1_PRU0_GPO9";
    ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT29.$suggestSolution = "PRG1_PRU0_GPO10";
    ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT30.$suggestSolution = "PRG1_PRU1_GPO9";
    ethercat1.PRU_ICSSG1_IEP.EDIO_DATA_IN_OUT31.$suggestSolution = "PRG1_PRU1_GPO10";

    I tried putting together a sysconfig using the pinmux configuration tool according to the 3 Ethernet interfaces you require (2x ICSSG1 using MII, 1x CPSW using RMII), and there does not seem to be a conflict with CPSW signals - see the below sysconfig. 

    /**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM64x" --package "ALV" --part "Default"
 * @versions {"tool":"1.17.0+3128"}
 */

/**
 * These are the peripherals and settings in this configuration
 */
const iCPSW1                = scripting.addPeripheral("CPSW");
iCPSW1.$useCase             = "CPSW_6";
iCPSW1.$name                = "MyCPSW1";
const iPRU_ICSSG1_MII_G_RT1 = scripting.addPeripheral("PRU_ICSSG1_MII_G_RT");
iPRU_ICSSG1_MII_G_RT1.$name = "MyPRU_ICSSG1_MII_G_RT1";

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
iCPSW1.$suggestSolution                            = "CPSW";
iCPSW1.RMII1_CRS_DV.$suggestSolution               = "PRG0_PRU1_GPO19";
iCPSW1.RMII1_RXD0.$suggestSolution                 = "PRG0_PRU1_GPO7";
iCPSW1.RMII1_RXD1.$suggestSolution                 = "PRG0_PRU1_GPO9";
iCPSW1.RMII1_RX_ER.$suggestSolution                = "PRG0_PRU0_GPO9";
iCPSW1.RMII1_TXD0.$suggestSolution                 = "PRG0_PRU1_GPO10";
iCPSW1.RMII1_TXD1.$suggestSolution                 = "PRG0_PRU1_GPO17";
iCPSW1.RMII1_TX_EN.$suggestSolution                = "PRG0_PRU1_GPO18";
iCPSW1.RMII_REF_CLK.$suggestSolution               = "PRG0_PRU0_GPO10";
iPRU_ICSSG1_MII_G_RT1.$suggestSolution             = "PRU_ICSSG1_MII_G_RT";
iPRU_ICSSG1_MII_G_RT1.MII_MT0_CLK.$suggestSolution = "PRG1_PRU0_GPO16";
iPRU_ICSSG1_MII_G_RT1.MII0_TXEN.$suggestSolution   = "PRG1_PRU0_GPO15";
iPRU_ICSSG1_MII_G_RT1.MII0_TXD3.$suggestSolution   = "PRG1_PRU0_GPO14";
iPRU_ICSSG1_MII_G_RT1.MII0_TXD2.$suggestSolution   = "PRG1_PRU0_GPO13";
iPRU_ICSSG1_MII_G_RT1.MII0_TXD1.$suggestSolution   = "PRG1_PRU0_GPO12";
iPRU_ICSSG1_MII_G_RT1.MII0_TXD0.$suggestSolution   = "PRG1_PRU0_GPO11";
iPRU_ICSSG1_MII_G_RT1.MII0_RXDV.$suggestSolution   = "PRG1_PRU0_GPO4";
iPRU_ICSSG1_MII_G_RT1.MII_MR0_CLK.$suggestSolution = "PRG1_PRU0_GPO6";
iPRU_ICSSG1_MII_G_RT1.MII0_RXD3.$suggestSolution   = "PRG1_PRU0_GPO3";
iPRU_ICSSG1_MII_G_RT1.MII0_RXD2.$suggestSolution   = "PRG1_PRU0_GPO2";
iPRU_ICSSG1_MII_G_RT1.MII0_CRS.$suggestSolution    = "PRG1_PRU0_GPO10";
iPRU_ICSSG1_MII_G_RT1.MII0_RXER.$suggestSolution   = "PRG1_PRU0_GPO5";
iPRU_ICSSG1_MII_G_RT1.MII0_RXD1.$suggestSolution   = "PRG1_PRU0_GPO1";
iPRU_ICSSG1_MII_G_RT1.MII0_RXD0.$suggestSolution   = "PRG1_PRU0_GPO0";
iPRU_ICSSG1_MII_G_RT1.MII0_COL.$suggestSolution    = "PRG1_PRU0_GPO9";
iPRU_ICSSG1_MII_G_RT1.MII0_RXLINK.$suggestSolution = "PRG1_PRU0_GPO8";
iPRU_ICSSG1_MII_G_RT1.MII_MT1_CLK.$suggestSolution = "PRG1_PRU1_GPO16";
iPRU_ICSSG1_MII_G_RT1.MII1_TXEN.$suggestSolution   = "PRG1_PRU1_GPO15";
iPRU_ICSSG1_MII_G_RT1.MII1_TXD3.$suggestSolution   = "PRG1_PRU1_GPO14";
iPRU_ICSSG1_MII_G_RT1.MII1_TXD2.$suggestSolution   = "PRG1_PRU1_GPO13";
iPRU_ICSSG1_MII_G_RT1.MII1_TXD1.$suggestSolution   = "PRG1_PRU1_GPO12";
iPRU_ICSSG1_MII_G_RT1.MII1_TXD0.$suggestSolution   = "PRG1_PRU1_GPO11";
iPRU_ICSSG1_MII_G_RT1.MII1_RXDV.$suggestSolution   = "PRG1_PRU1_GPO4";
iPRU_ICSSG1_MII_G_RT1.MII_MR1_CLK.$suggestSolution = "PRG1_PRU1_GPO6";
iPRU_ICSSG1_MII_G_RT1.MII1_RXD3.$suggestSolution   = "PRG1_PRU1_GPO3";
iPRU_ICSSG1_MII_G_RT1.MII1_RXD2.$suggestSolution   = "PRG1_PRU1_GPO2";
iPRU_ICSSG1_MII_G_RT1.MII1_CRS.$suggestSolution    = "PRG1_PRU1_GPO10";
iPRU_ICSSG1_MII_G_RT1.MII1_RXER.$suggestSolution   = "PRG1_PRU1_GPO5";
iPRU_ICSSG1_MII_G_RT1.MII1_RXD1.$suggestSolution   = "PRG1_PRU1_GPO1";
iPRU_ICSSG1_MII_G_RT1.MII1_RXD0.$suggestSolution   = "PRG1_PRU1_GPO0";
iPRU_ICSSG1_MII_G_RT1.MII1_COL.$suggestSolution    = "PRG1_PRU1_GPO9";
iPRU_ICSSG1_MII_G_RT1.MII1_RXLINK.$suggestSolution = "PRG1_PRU1_GPO8";

    It looks like the CPSW signal that you shared had a conflict could be alternatively configured with the following pins.

    Ball Name CPSW Signal Name
    PRG0_PRU0_GPO10
    		 RMII_REF_CLK
    PRG0_PRU0_GPO9
    		 RMII1_RX_ER
    PRG0_PRU1_GPO9
    		 RMII1_RXD1
    PRG0_PRU1_GPO10
    		 RMII1_TXD0

    For MDIO Pin Conflict:

    Using the above pinmux selection (in my attached sysconfig), I can see a conflict with adding MDIO for the ICSSG1 interfaces and CPSW RMII interface. 

    The ICSSG1 MDIO only has the option of using "PRG1_MDIO0_MDC" and "PRG1_MDIO0_MDIO"

    The CPSW MDIO has two options 

    MDC: "PRG1_MDIO0_MDC" or "PRG0_PRU1_GPO19"

    MDIO: "PRG1_MDIO0_MDIO" or "PRG0_PRU1_GPO18"

    However, "PRG0_PRU1_GPO19" is already used by CPSW's "RMII1_CRS_DV" signal and "PRG0_PRU1_GPO18" is already used by CPSW's "RMII1_TX_EN" signal.

    "RMII1_CRS_DV" cannot be changed to "PRG1_PRU1_GPO19" and "RMII1_TX_EN" cannot be changed to "PRG1_PRU1_GPO18" because these signals are part of IOSET1 and all other CPSW signals are part of IOSET2.

    According to the datasheet 7.10.5.1 CPSW3G,

    "CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more
    signals which can be multiplexed to more than one pin. Timing requirements and switching
    characteristics defined in this section are only valid for specific pin combinations known as IOSETs.
    Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G
    IOSETs section."

    I believe this means the specifications reported in the datasheet are only valid for the given IOSET configurations. If you choose to mix IOSETs for a given interface, we cannot guarantee the timing requirements and switching characteristics you would expect from the datasheet.

    Due to this reason, I think it's safer to go with your option 2. 

    Let me check with a colleague pn this as well since using CPSW with ICSSG in MII mode should be a common use case (especially for applications using EtherCAT) so frankly I'm surprised that there is such a pin configuration conflict.

    -Daolin