DRA821U-Q1: DRA821U-Q1, LPDDR4 configuration Tool

Hi Max,

Max Chen1 said:

We only need to set DDRSS0 values, ignore other DDRSS1-3 values, correct?

Correct. Note that the online (sysconfig) version will not even show inputs for DDRSS1-3 for DRA821.

https://dev.ti.com/sysconfig/?product=TDA4x_DRA8x_AM67x-AM69x_DDR_Config&device=J7200_DRA821_SR1.0_alpha 

Max Chen1 said:

Frequency Set0, Frequency Set 1 and Set 2 ?    what is set 0, set1 and set 2?  can we say set 0 min Frequency and set 1 max frequency?

FS0 is the boot frequency. This is typically 55 MHz or less.

FS1/FS2 should be set the same, and correspond to the operating frequency. Max value supported for DRA821 is 1600 MHz. 

Max Chen1 said:

WL set A and WL set B? do I have to set A and B? what about just set A?

I am not clear on the question. 

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As a small request - since this question is a follow-up to the existing thread, can you please use the existing thread(s) for follow-up questions as opposed to creating new tickets?

Thanks,
Kevin

I meant WLS options: WL SET A and WL SET B, which one should i choose ?currently it is WL set A for EVM.

Thanks

Max

If your memory datasheet and/or supplier does not indicate which write latency set to use, then I would suggest leaving it as set A.

Regards,
Kevin