We are facing a problem some times in SRIO IP initialization.
Issue details given below.
Issue: Sometimes SRIO Link between FPGA and DSP is not properly initialized (PORT_OK bit in DSP status register is not set). Whenever this state happens, when reset is given to FPGA alone (without any change in state of DSP) by pressing FPGA reset manually (through PUSH Button), issue seems to be solved. i.e. SRIO link gets up and doorbell is coming properly.
During this state DSP is waiting in while loop (observed in JTAG mode) for the srio initialization from FPGA. This is occurring randomly.
During the issue occurence, we have enabled Signal tap for FPGA SRIO IP signals (port_initialized & Port_error) and observed that port initialized is not set to high. It is low. After giving FPGA reset manually as mentioned above, port_initialized signal goes to high and process continues.
Please provide us any pointers for the issue resolution
We are using Altera FPGA Device: EP4SGX360KF43I4 DSP TI device: TMS320C6678
We are using 1x-serial mode for SRIO. Lane number is 1 and lane rate is 2.5Gbps.
Power up sequence in FPGA and DSP (both in JTAG mode):
Step 1: Board power-ON.
Step 2. FPGA image loaded.
Step 3. FPGA starts running.
Step 4. DSP image loaded.
Step 5. DSP starts running.
Step 6. DSP will give SRIO start address, doorbell configuration to FPGA.
Step 7. FPGA will give reset to DSP upon running SRIO for 3 seconds.
Step 8. FPGA and DSP will get soft-reset.
Step 9. DSP gets reloaded.
Step 10. DSP will give SRIO start address, doorbell configuration to FPGA.
Step 11. Data transmission via SRIO gets start between FPGA and DSP.
Power up sequence in FPGA and DSP (both in Flash mode):
1. Board power-ON.
2. FPGA and DSP images configured from Flash.
3. FPGA and DSP starts running.
4. DSP will give SRIO start address, doorbell configuration to FPGA.
5. FPGA will give reset to DSP upon running SRIO for 3 seconds.
6. FPGA and DSP will get soft-reset.
7. DSP gets reloaded from Flash.
8. DSP will give SRIO start address, doorbell configuration to FPGA.
9. Data transmission via SRIO gets start between FPGA and DSP.
DSP Micro level Power-up sequence:
Step 1: Set SRIO power domain to ON.(Default it would be off to save power consumption and thermal stability)
Step 2: Enable the clock for SRIO. Clock here refers to reference clock for serdes module (SRIO's transceiver).
Step 3: Start the state transition for module by setting GO bit in PSC command register. Implementation for enable power and clock for a module inside DSP requires 2 steps.
a. Setting which state to enter next b. set go bit in the PSC register
Step 4: Wait for state transition to complete
Step 5: Disable all the blocks inside SRIO and set boot complete to 0. DSP SRIO consists of 9 logical blocks. We are disabling and enabling the logical blocks(LSUs, RXUs, MAUs, Data Path 0,1,2,3) inside DSP.
Step 6: Enable the blocks
Step 7: Configure the SRIO mode and line rate
Step 8: Configure PE features and Operational capability
Step 9: Set Host and destination device ID and TLM registers
Step 10: Enable the ports and configure port related registers
Step 11: Set boot complete and check for SRIO Port OK in error stat register.
