• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 2 answers
  • Subscribers 102 subscribers
  • Views 801 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x I/O set violation

Aron Phillips
Prodigy 30 points
Other Parts Discussed in Thread: AM3358

I am uncertain as to where I would get a good explanation for my problem. I designed a board that uses the AM3358 and I did not use the pin mux tool to guarantee that I would be using a "proper" pin mux. I just grabbed the proper peripheral pin as stated from the datasheet as I assumed that any combination could be used. I was told by the programmer for the board that the use of the pins that I chose were incorrect because it violated the IO Sets (I used a tx pin from say IO_Set 3 and an rx pin from IO_Set 5 for UART - just as an example).

Of which I am not certain, if I happened to have violated the IO Sets, what is the real consequence? Does the TI chip actually prevent the functions from working if it is in violation of the sets? I am only familiar with the peripheral functions of the NXP, STM, and Atmel chips. Those chips allow for any combination that can be conceived.

  • 0
    TI__Guru*** 125430 points

    Aron Phillips said:
    I was told by the programmer for the board that the use of the pins that I chose were incorrect because it violated the IO Sets

    Have you verified this information through use of the Pin Mux Tool?

    Aron Phillips said:
    Of which I am not certain, if I happened to have violated the IO Sets, what is the real consequence?

    The consequence is that we won't be able to guarantee the corresponding timings will be within spec across process, voltage, and temperature.

  • 0 in reply to Brad Griffis
    TI__Guru 55885 points

    All signals of each peripheral interface must have their timing parameter values adjusted to match the values defined in the data sheet. This is done when the SOC is being designed. There was no attempt made to close timing of any signal combinations that are not defined as valid IOSETs.  Therefore, you need to redesign your product such that all peripheral interfaces use defined IOSETs.

    Regards,
    Paul