AM5748: DDR ECC issue in U-boot

Michael Krummsdorf

Part Number: AM5748

Hello,

we are having issues enabling ECC in U-Boot 2019.04 on our custom AM5748 board.
We use the Excel sheet v2.0.2 for the values.

So far, without ECC enabled the board boots fine. But with ECC enabled via emif_ecc_ctrl_reg U-Boot hangs on relocation to DRAM:

RAM Configuration:
Bank #0: 80000000 2 GiB
Bank #1: 0 0 Bytes

DRAM: 2 GiB
initcall: 808110b9
New Stack Pointer is: fcf42eb0
initcall: 80811231
initcall: 80811305
initcall: 80811309
initcall: 808111d9
Relocation Offset is: 7e753000
Relocating to fef53000, new gd at fcf42ed8, sp at fcf42eb0

The only modification is

.emif_ecc_ctrl_reg = 0xD0000001, [according to https://e2e.ti.com/support/processors/f/791/t/756526]

What could be the cause for the crash? Could the timing with ECC be wrong while working fine without ECC?

Please advise any more information needed.

Thanks,

Michael

over 5 years ago

0 Krunal Bhargav34 over 5 years ago

TI__Mastermind 43885 points

Hello Michael,

I am wondering if you could please share your lisa_map and emif_ecc_address_range configuration from the Uboot.

Regards,
Krunal

0 Michael Krummsdorf over 5 years ago in reply to Krunal Bhargav34

Intellectual 320 points

Hello Krunal,

of course I can.
This is the lisa_map configuration:

static const struct dmm_lisa_map_regs tqma574x_lisa_regs = {
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};

And the emif_ecc_address_range embedded in struct emif_regs:

static const struct emif_regs tqma574x_emif1_ddr3_666mhz_emif_regs = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x1000514D,
.ref_ctrl_final = 0x10000A25,
.sdram_tim1 = 0xD11367EC,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x407F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,
.emif_rd_wr_exec_thresh = 0x00000305,
#if CONFIG_TQMA57XX_ECC
.emif_ecc_ctrl_reg = 0xD0000001,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000,
#endif
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x006B006B,
.emif_ddr_ext_phy_ctrl_3 = 0x006B006B,
.emif_ddr_ext_phy_ctrl_4 = 0x006B006B,
.emif_ddr_ext_phy_ctrl_5 = 0x006B006B
};

The symbol is defined via defconfig: CONFIG_TQMA57XX_ECC=y

Michael

0 Krunal Bhargav34 over 5 years ago in reply to Michael Krummsdorf

TI__Mastermind 43885 points

Hi Michael,

Please correct me if I am wrong but it seems like you have one EMIF (2Gb) and ECC is only supported on 1Gb. Based on the previous information, the emif_ecc_ctrl_reg and emif_ecc_address_range looks correct. However, the lisa_map configuration does not look correct to me.

If ECC is enabled, interleaving should be disabled. Please try the following lisa_map configuration:

.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x0,
.dmm_lisa_map_3 = 0x80700100,

Regards,
Krunal

0 Michael Krummsdorf over 5 years ago in reply to Krunal Bhargav34

Intellectual 320 points

Hi Krunal,

actually we have 1 Gb on EMIF1 with 512 Mb ECC and 1 Gb on EMIF2.

Inspired by your post we discussed the lisa_map settings again and finally found working values:

static const struct dmm_lisa_map_regs tqma574x_lisa_regs = {
.dmm_lisa_map_2 = 0xc0600200, /* 1GiB on EMIF2 */
.dmm_lisa_map_3 = 0x80600100, /* 1GiB on EMIF1 */
.is_ma_present = 0x1
};

Do you approve these settings?
Is there a requirement to assign EMIF1 to the highest priority lisa_map_3?

Why does the Excel table give the very confusing value:
.dmm_lisa_map_3 = 0xFF020100,

Trying to understand that took a whole lot of time and in the end we dropped it.

Regards, Michael

0 Krunal Bhargav34 over 5 years ago in reply to Michael Krummsdorf

TI__Mastermind 43885 points

Hello Michael,

Based on my internal discussion, there isn’t a requirement on which EMIF you put on which priority. Also, there are some values that the spreadsheet produces which may not apply to all use cases, and it will be fixed in a future release.

Regards,
Krunal

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AM5748: DDR ECC issue in U-boot