Compiler/PROCESSOR-SDK-DRA7X: Use HDMI clock for LVDS output

Hi Raghu,

I think someone is overwriting this register. Do you call this API somewhere also?

I remember you had partitioned code, so some part of the code runs in fast boot, the other part run in actual usecase.. Do you have to or by mistake calling this API multiple times?

Rgds,

Brijesh

Hi Brijesh,

I have made below changes in DisplayCtrl. and then I have read the register. I think now clock is set to HDMI. Can you please confirm . 

root@mmt2020-a880:~#
root@mmt2020-a880:~# omapconf read 0x4A002538
000002C8
root@mmt2020-a880:~# omapconf read 0x58000040
00011000
root@mmt2020-a880:~#

/**
*******************************************************************************
*
* \brief Configures the clock source and Video PLL
*
* \param vencId [IN] Venc ID.
* \param pixelClock [IN] Pixel CLock Value.
* \param divisorPCD [IN] Pixel clock divisor value.
*
*******************************************************************************
*/
void DisplayCtrlLink_configureVideoPllAndClkSrcForLCD(
UInt32 vencId, UInt32 pixelClock,UInt32 divisorPCD)
{
Bsp_PlatformSetPllFreq vPllCfg;
Bsp_PlatformVencSrc vencClkCfg;
Int32 status = SYSTEM_LINK_STATUS_SOK;

/*
* For LCD resolution 800x480@60fps pixelClock = 29.232Mhz
* PixelCLock is computed as follows -
* No. of pixels per frame = (800 + H blanking) * (480 + Vertical blanking
* = 928*525 = 487200
*For 60fps i.e 60 * 487200 = 29232000. i.e 29232 KHz.
*/
vPllCfg.videoPll = BSP_PLATFORM_PLL_VIDEO1;

if(Bsp_platformIsTda3xxFamilyBuild())
{
vPllCfg.videoPll = BSP_PLATFORM_PLL_EVE_VID_DSP;
}

/*
* HPixel clock to be configured. based on the PCD divisor.
* This is the value for which the VideoPLL can lock.
* TODO: Currently from usecase divisor is being set as 4. This is due to a
* defect in BSP - PLL not locking for 29232 * 1. Once this issue is
* resolved divisorPCD can be set to 1
*/
vPllCfg.pixelClk = pixelClock * divisorPCD;
vPllCfg.chooseMaxorMinMN = (UInt32) BSP_PLATFORM_VIDEO_PLL_CALC_MAX_MN;

status = Bsp_platformSetPllFreq(&vPllCfg);
UTILS_assert (status == SYSTEM_LINK_STATUS_SOK);

switch(vencId)
{
case SYSTEM_DCTRL_DSS_VENC_LCD1:
case SYSTEM_DCTRL_DSS_VENC_SDTV:
vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD1;
vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT1;
if(Bsp_platformIsTda3xxFamilyBuild())
{
vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_EVE_VID_DSP;
}
break;

case SYSTEM_DCTRL_DSS_VENC_LCD2:
vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD2;
// vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT3;
vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_HDMI;
break;

case SYSTEM_DCTRL_DSS_VENC_LCD3:
vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD3;
vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT3;
break;

default:
UTILS_assert((Bool)0U);
break;
}

status = Bsp_platformSetVencClkSrc(&vencClkCfg);
UTILS_assert (status == SYSTEM_LINK_STATUS_SOK);

}

Regards,

Raghu