AM6548: Meaning of TSTAMP_EN bit for NAVSS0 and PCIE0/1 CPTS instances

Dominic, 

Not sure I am following you on this issue. I looked up:

1. CPTS_CONTROL_REG (NAVSS)
2. CPSW_CPTS_CONTROL_REG (MCU_CPSW)
3. PCIE_CPTS_CONTROL_REG (PCIe)

Bit 3 of these registers defines the TSTAMP_EN bit, where the definition is the same across all three subsystems. It is an ENABLE bit. 

You may get confused with the following paragraph in CPSW. It is actually describing the Transmit function, where it should say:

"The host sets the TSTAMP_EN bit, [then the host] sends the DOMAIN, MESSAGE_TYPE, and SEQUENCE_ID in the additional ..." 

Note that i added a few words in the "[]". What is really saying is that once the TSTAMP_EN bit is set to one, the CPSW reports back the actual timestamp the TX packet left for wire, so the host know the exact timestamp inserted to the PTP packet. 

Let me know if these notes clears up. 

regards

Jian

12.2.1.4.7.15 Host Transmit Event
The host can send a packet to be transmitted on an Ethernet port that will generate a time synchronization
event. The host sets the TSTAMP_EN bit and sends the DOMAIN, MESSAGE_TYPE, and
SEQUENCE_ID in the additional control information that resides in the protocol specific section of the
descriptor that is transmitted to the CPSW_2G. An event is then generated and placed on the event FIFO
once the packet is transmitted. Host events allow the user to timestamp exactly when a software
generated packet exits the device.

Hello Jian,

that's not really what I was wondering about. I can make some sense out of the TSTAMP_EN bit in the context of the CPSW_CPTS, but what does that bit mean for the other two CPTS variants (NAVSS and PCIe?)

I was "hoping" that the TSTAMP_EN bit might be a "domain specific" timestamping mechanism, i.e. "packet received/sent" in the context of the CPSW_CPTS, and maybe "ptm dialog completed" in the PCIE_CPTS, but unfortunately right now I believe the bit is only meaningful in the context of the CPSW_CPTS.

The thing about the CPSW description is just that the bit is described as "Host Receive time stamp Enable", whereas the functional description mentions it in the context of the "Host Transmit Event". I'm not sure how that is different from the "12.2.1.4.7.13.5.2 Ethernet Port Transmit Event" and 12.2.1.4.7.13.5.1 Ethernet Port Receive Event, but for now we're not interested in the CPSW at all.

Regards,

Dominic

Move email discussions to e2e upon unlocking:

Sent: Thursday, December 17, 2020 2:34 AM

Hello Jian,

at the time when I created this thread I was hoping that this TSTAMP_EN bit was the magic key that could solve my issue about PTP.

I've since then come to the conclusion that this is most likely left-over from the CPSW CPTS, as I've already expressed in my last post.

I was just looking for confirmation, since only TI would know for sure. It would be great if you could confirm with your IP colleagues whether this bit has any meaning for NAVSS and PCIe CPTS.

Dominic Rath

> Dominic,

>

>

>

> I was in the middle of typing when the thread was locked. So I will email you directly for now.

>   https://e2e.ti.com/support/processors/f/791/t/924477

> first I apologize for the extended delay. The TSTAMP_EN bit seems to

> be specific to CPSW interface signals when it is integrated in the

> CPTS, as there separate _EN bits for HWPUSH events that is used in NAV

> and PCIe. CPTS was initially built to support IEEE1588, thus it has a module that ties to CPSW directly to stamp packets instantly.

> Let me confirm with IP designer and will send you an update within this week.

> (if you are still thinking of use a similar bit dynamically to

> enable/disable stamping – that is not the intension of the IP:)

> Jian

Dominic, 

The IP owner is on vacation and will be back next week. So i will report back next week when he confirms. 

Jian