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TMS320C6674: custom PCIe board & bus reset

Part Number: TMS320C6674
Other Parts Discussed in Thread: XIO2000A


We are having C6674 based custom PCIe board. We are trying to use the device in Linux KVM/Qemu virtual machine. So on the host Linux machine, there are vfio kernel modules. When virtual machine is started vfio calls Linux kernel pci_try_reset_bus ( to do bus reset. At this point device disappears. Lspci on the host shows:


# lspci -v -s 11:00.0

11:00.0 Multimedia controller: Texas Instruments Device b005 (rev ff) (prog-if ff)

        !!! Unknown header type 7f

        Kernel driver in use: vfio-pci


PCI config space looks to be just 0xffff ffff.

 If “quirk” is added to Linux kernel drivers/pci/quirk.c to prevent bus reset


DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);


Device shows up in the virtual machine and can be accessed.

Should C6674 support bus reset over PCIe? Or any idea what might be wrong?

Br, Antti

  • Hi 

    We are still looking into this. Any update or break through from  your side? Any additional debug logs to share. 
    A quick question for you - do you see any device interrupts on c6674 when you do the bus reset via the linux host?


  • Hi,

    Thanks for update. Unfortunately Linux Kernel doesn't have much debug logs when doing bus reset. Is there something that we can look with the JTAG / CCS from the device itself?

    We are not seeing device interrupts when doing the bus reset.

    Br, Antti 

  • Hi Antti

    Sorry for the delay, after some internal digging through specifications my understanding from the subsystem specs is that hot reset event needs subsystem to be reset by software.  I do not think TI provided software is not resetting PCIe subsystem based on hot reset. 

    So it is appears that we really do not support hot reset functionality 

    I think it maybe best to see if it is possible to prevent upstream from sending a PCIe hot reset. 



  • Hi Mukul,

    Thanks for the info.

    Adding one line in Linux kernel drivers/pci/quirk.c prevents bus reset.

    DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 

    So would it be possible that TI submits this as a patch to Linux kernel?

    Br, Antti

  • Hello Antti, 

    Sorry I forgot to post the response on this after talking to the linux team on this. 

    Here are few information bytes going  by git blame.

    One quirk for the TI XIO2000a PCIe-PCI Bridge is by NI

    commit 1f56f4a2b4d12c1c348cab23024024396ec7cddc
    Author: Gabe Black <>
    Date:   Tue Oct 6 09:19:45 2009 -0500

        PCI quirk: TI XIO200a erroneously reports support for fast b2b transfers
        This quirk will disable fast back to back transfer on the secondary bus
        segment of the TI Bridge.
        Signed-off-by: Gabe Black <>
        Signed-off-by: Jesse Barnes <>

    And the other quirk is by TI

    commit 63c4408074cbcc070ac17fc10e524800eb9bd0b0
    Author: Hemant Pedanekar <>
    Date:   Tue Apr 5 12:32:50 2011 +0530

        PCI: Add quirk for setting valid class for TI816X Endpoint
        TI816X (common name for DM816x/C6A816x/AM389x family) devices configured
        to boot as PCIe Endpoint have class code = 0. This makes kernel PCI bus
        code to skip allocating BARs to these devices resulting into following
        type of error when trying to enable them:
        "Device 0000:01:00.0 not available because of resource collisions"
        The device cannot be operated because of the above issue.
        This patch adds a ID specific (TI VENDOR ID and 816X DEVICE ID based)
        'early' fixup quirk to replace class code with
        Signed-off-by: Hemant Pedanekar <>
        Signed-off-by: Jesse Barnes <>

    Given that PCIESS automatically disables LTSSM, it should be fine to add quirk_no_bus_reset.

    May we request you to directly upstream this since have working setup and you are able to reproduce the issue. (Like NI sent a patch for TI device).

    I will currently not be able to commit TI submitting any patches on this directly.

    Sorry for the inconvenience. I hope this helps.



  • We have still technical questions about hot reset support. Is it documented somewhere that C6674 doesn’t support hot reset over PCIe? Or is this some new finding, which is not yet added to errata?

    Accroding to KeyStone Architecture Peripheral Component Interconnect Express (PCIe) chapter 1.4.4

    The PCIESS supports the conventional reset mechanism that is specified within the PCI Express Specification.

     And PCI Express® Base Specification Revision 2.0 chapter Terms and Acronyms says

     Conventional Reset    A Hot, Warm, or Cold reset. Distinct from Function Level Reset (FLR).

    We appreciate if TI would upstream this, if it is 100% sure that there is no hot reset on C6674 over PCIe.

    Br, Antti

  • There is no hot reset on c6674. It is not a new finding looking through the archives , but looks like this seems to be a miss in terms of carrying it over to errata. I am unable to trace the reasons on why this never made it to the errata ( the user guide will reflect the expected functional behavior and is correct, the errata - advisory or usage note sections should've captured this limitation). 

    Again no plans for TI to up-stream.

    We are not undertaking any new software development/enhancements for this device family.

    We will only evaluate software bug fixes that are critical on need basis weighed in by business opportunity. 

    I regret the inconvenience this may cause. 

    I will investigate the corrective action on errata - and see if that can be updated some time next quarter post my investigation.