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DRA821U: How to change the initial MPU (A72) clock frequency in SBL

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821, SYSBIOS

Could you tell me how to change the initial MPU (A72) clock frequency in SBL?

Our customer has modified the SBL source code to change the initial MPU (A72) clock frequency, but the MPU was not running.

They modified the sbl_soc_cfg.h as follows to change the initial MPU clock frequency.

~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h

#if defined (SOC_J7200)
:
:
#define SBL_MPU1_CPU0_FREQ_HZ (1500000000)

They modified the sbl_slave_core_boot.c as follows to make sure that each core clock frequency was changed.

~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c

void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry, uint32_t requestCoresFlag)
{
uint64_t respFreq, currentFreq;
:
:
status = Sciclient_pmQueryModuleClkFreq (
sblSlaveCoreInfoPtr->tisci_dev_id,
sblSlaveCoreInfoPtr->tisci_clk_id,
sblSlaveCoreInfoPtr->slave_clk_freq_hz,
&respFreq,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_MAX, " Sciclient_pmQueryModuleClkFreq...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
else
{
SBL_log(SBL_LOG_MAX, "Sciclient_pmQueryModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, respFreq);
}
SBL_ADD_PROFILE_POINT;

SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, sblSlaveCoreInfoPtr->slave_clk_freq_hz);
SBL_ADD_PROFILE_POINT;
status = Sciclient_pmSetModuleClkFreq(sblSlaveCoreInfoPtr->tisci_dev_id,
sblSlaveCoreInfoPtr->tisci_clk_id,
sblSlaveCoreInfoPtr->slave_clk_freq_hz,
TISCI_MSG_FLAG_AOP,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_MAX, " Sciclient_pmSetModuleClkFreq...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
SBL_ADD_PROFILE_POINT;

status = Sciclient_pmGetModuleClkFreq(
sblSlaveCoreInfoPtr->tisci_dev_id,
sblSlaveCoreInfoPtr->tisci_clk_id,
&currentFreq,
SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
SBL_log(SBL_LOG_MAX, " Sciclient_pmGetModuleClkFreq...FAILED \n");
SblErrLoop(__FILE__, __LINE__);
}
else
{
SBL_log(SBL_LOG_MAX, "Sciclient_pmGetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, currentFreq);
}
SBL_ADD_PROFILE_POINT;

8.4.3. Setting the clock for a device
software-dl.ti.com/.../faq_module_clocking.html

They used the SBL test application to make sure the MPU was running. In the output message log, the MPU clock frequency is set to 1.5GHz, but "MPU1_0 running" is not output.

~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/example/k3MulticoreApp/binary/j7200/sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release.appimage

SBL_log_2.0GHz_debug.txt
SBL Revision: 01.00.10.00 (Apr 26 2021 - 17:23:32)
TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Searching for X509 certificate ...not found
Switching core id 4, proc_id 0x1 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 4
Disabling HW-based memory init of MCU TCMs for core 4
Sciclient_procBootSetProcessorCfg enabling TCMs...
Copying 0x40 bytes to 0x41010000
Copying 0x2c88 bytes to 0x41010100
Copying 0x500 bytes to 0x41015980
Copying 0x28 bytes to 0x41015e80
Copying 0x10 bytes to 0x41015ea8
Copying 0x13f40 bytes to 0x41c9c320
Copying 0x6e50 bytes to 0x41cb0260
Copying 0x1500 bytes to 0x41cbac00
Copying 0xb30 bytes to 0x41cbc100
Setting entry point for core 4 @0x41010000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0x688 bytes to 0x70024000
Copying 0x44 bytes to 0x70024688
Setting entry point for core 0 @0x70024000
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70024000...
Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
MPU1_0 running
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Sciclient_pmGetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciserver Built On: Nov  5 2020 22:47:06
Starting Sciserver..... PASSED

SBL_log_1.5GHz_debug.txt
SBL Revision: 01.00.10.00 (Apr 26 2021 - 16:40:31)
TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Searching for X509 certificate ...not found
Switching core id 4, proc_id 0x1 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 4
Disabling HW-based memory init of MCU TCMs for core 4
Sciclient_procBootSetProcessorCfg enabling TCMs...
Copying 0x40 bytes to 0x41010000
Copying 0x2c88 bytes to 0x41010100
Copying 0x500 bytes to 0x41015980
Copying 0x28 bytes to 0x41015e80
Copying 0x10 bytes to 0x41015ea8
Copying 0x13f40 bytes to 0x41c9c320
Copying 0x6e50 bytes to 0x41cb0260
Copying 0x1500 bytes to 0x41cbac00
Copying 0xb30 bytes to 0x41cbc100
Setting entry point for core 4 @0x41010000
Sciclient_pmSetModuleState On, DevId 0x4...
Copying 0x688 bytes to 0x70024000
Copying 0x44 bytes to 0x70024688
Setting entry point for core 0 @0x70024000
Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70024000...
Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1500000000Hz...
Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1500000000Hz...
Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1500000000Hz...
Sciclient_pmSetModuleState Off, DevId 0xca...
Sciclient_pmSetModuleState On, DevId 0xca...
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Sciclient_pmGetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciserver Built On: Nov  5 2020 22:47:06
Starting Sciserver..... PASSED

5.2.7. Testing the SBL
software-dl.ti.com/.../boot_k3.html

Best regards,

Daisuke

  • Dear TI support team,

    Is it correct how to change the initial MPU (A72) clock frequency described in above post?

    Could you point me out if I have any misunderstandings?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    #define SBL_MPU1_CPU0_FREQ_HZ (1500000000)

    Similar to that please change:

    #define SBL_MPU1_CPU1_FREQ_HZ       (1500000000)

    It is possible that 1.5GHz might not be straight forward to get so can you try 1.2GHz? i.e

    #define SBL_MPU1_CPU1_FREQ_HZ       (1200000000)
    #define SBL_MPU1_CPU0_FREQ_HZ       (1200000000)

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    Unfortunately, our customer is on vacation called the Golden Week in Japan so they can not try your suggestion for a week or so. We also can not try it because we do not have a DRA821 board.

    On the other hand, our customers have already tried the frequencies listed below.

    1.9GHz, 1.8GHz, 1.7GHz, 1.6GHz, 1.5GHz, 1GHz

    At 1.6GHz and lower frequencies, "MPU1_0 running" is not output. At 1.7GHz and higher frequencies, "MPU1_0 running" is output, but their benchmark application for MPU shows the same result as 2GHz.

    Best regards,

    Daisuke

  • Hi Keerthy-san,

    > It is possible that 1.5GHz might not be straight forward to get so can you try 1.2GHz? i.e

    Could you tell me why it is suggested to try 1.2GHz?

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    I have tried 1.2GHz and it works that is why i suggested that.

    I believe 1.5GHz in particular has an issue that i had observed on J721e and i checked on j7200 as well
    & i saw the issue.

    I am trying on Linux & so on SBL you should set this register address: 0x688040 to value 0x80000001 in SBL.

    The above will enable you to rightly set 1.5GHz.

    Can you try that and let me know? "Verify Answer" if the above suggestions solve the problem.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    > I am trying on Linux & so on SBL you should set this register address: 0x688040 to value 0x80000001 in SBL.

    This sets the value to PLL8_SS_CTRL register. MAIN PLL registers are defined in cslr_main_pll_mmr.h, but those definitions do not seem to be used in any source code.

    Which source code should we modify to set this?

    This sets BYPASS_EN in PLL8_SS_CTRL register to 1b and bypasses the SS modulator.

    Why is the spread spectrum modulation disabled? Should the spread spectrum modulation not be used for PLL8 (MPU clock)?

    Best regards,

    Daisuke

  • Hi Daisuke-San,

    By default the register reads 0x80000000

    I.e PLL8_SS_CTRL bit[0] only needs to be set.

    There is a mux in the A72 PLL clock path that selects the PLL output OR the HSDIV output. In order to use the HSDIV output for the A72 PLL, please set bit 0 of 0x688040 (from 0) to 1.

    So what i am suggesting is to do:

    CSL_REG32_WR(0x688040, 0x80000001);

    Before you call the below function to set clock frequency.

    Sciclient_pmSetModuleClkFreq

    It is a hack to get the right clock frequency. Is it possible for you to try that & get back?

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    > There is a mux in the A72 PLL clock path that selects the PLL output OR the HSDIV output. In order to use the HSDIV output for the A72 PLL, please set bit 0 of 0x688040 (from 0) to 1.

    I confirmed it in Figure 5-759 of TRM.

    Our customer will try your suggestion.

    Can your suggestion be used at frequencies other than 1.5GHz, regardless of clock frequency?

    Best regards,

    Daisuke

  • Hi Daisuke-San,

    I have tried 1.2GHz. I believe we can try others as well. If no other questions. Please click on verify answer.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    Our customer supposes that failing to change the MPU clock frequency is a software issue and they suspect that the current SDK is incomplete.

    At least the SDK should support the clock frequencies for all devices (OPPs).

    Does the current SDK only support the maximum clock frequency for DRA821xT?

    If so, is there a plan that a future SDK supports the clock frequencies for all devices (OPPs)?

    Best regards,

    Daisuke

  • Does the current SDK only support the maximum clock frequency for DRA821xT?

    That is correct. It boots at 2 GHz.


    If so, is there a plan that a future SDK supports the clock frequencies for all devices (OPPs)?

    I will get back to you once I hear from the internal team.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply. I'm sorry to ask you many times.

    You suggested in the above post to define both cores in MPU subsystem to the same frequency to change the MPU clock frequency.

    #define SBL_MPU1_CPU1_FREQ_HZ (1200000000)
    #define SBL_MPU1_CPU0_FREQ_HZ (1200000000)

    Setting each core clock frequency in the SBL is only done if there is a valid application image for each core.

    Is it needed to define for both MPU cores even if only one MPU core is used?

    Is an application image needed for each of both MPU cores even if only one MPU core is used?

    Best regards,

    Daisuke

  • Hi Daisuke-San,

    By default it works in SMP mode that is when you need to set both cores.

    If you are using CPU0 alone then only try with:

    #define SBL_MPU1_CPU0_FREQ_HZ (1200000000)

    Can you confirm that you are now able to boot with 1.2 GHz?

    Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    Our customer is able to boot with 1.2GHz, but their benchmark application for MPU shows the same result as 2GHz.

    By the way, the benchmark application shows different results depending on the frequency in the case of AM654x.

    Best regards,

    Daisuke

  • Hi Daisuke-San,

    Can the customer share the output of the below command:

    k3conf dump clock 202

    The above will confirm if the A72 is indeed running at 1.2GHz.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    Our customer is using the RTOS SDK not Linux. The clock read by Sciclient_pmGetModuleClkFreq shows 1.2GHz.

    SBL_log.txt
    SBL Revision: 01.00.10.00 (May 17 2021 - 14:52:48)
    TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
    SCISERVER Board Configuration header population... PASSED
    Sciclient_setBoardConfigHeader... PASSED
    Initlialzing PLLs ...done.
    InitlialzingClocks ...done.
    Initlialzing DDR ...done.
    Initializing GTC ...Begin parsing user application
    Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
    Searching for X509 certificate ...not found
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x798 bytes to 0x90000800
    Copying 0x2a8 bytes to 0x90100000
    Copying 0x1c5c0 bytes to 0x90200000
    Copying 0x3618 bytes to 0x9021c5c0
    Copying 0x23298 bytes to 0x90220000
    Setting entry point for core 0 @0x90100000
    Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x90100000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    PLL8_SS_CTRL Register Value = 0x80000001
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmSetModuleState Off, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x7a0 bytes to 0x70040000
    Copying 0xe3a0 bytes to 0x80000000
    Copying 0x18c bytes to 0x8000e3a0
    Copying 0x2290 bytes to 0x8000e530
    Copying 0x498 bytes to 0x800107c0
    Copying 0x9e68 bytes to 0x80010c58
    Setting entry point for core 1 @0x80009730
    Sciclient_procBootSetProcessorCfg, ProcId 0x21, EntryPoint 0x80009730...
    Sciclient_pmQueryModuleClkFreq, DevId 0xcb @ 1200000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xcb @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xcb @ 1200000000Hz...
    Sciclient_pmSetModuleState Off, DevId 0xcb...
    Sciclient_pmSetModuleState On, DevId 0xcb...
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Enabling MCU TCMs after reset for core 4
    Disabling HW-based memory init of MCU TCMs for core 4
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Copying 0x40 bytes to 0x41010000
    Copying 0x2c88 bytes to 0x41010100
    Copying 0x500 bytes to 0x41015980
    Copying 0x28 bytes to 0x41015e80
    Copying 0x10 bytes to 0x41015ea8
    Copying 0x13f40 bytes to 0x41c9c320
    Copying 0x6e50 bytes to 0x41cb0260
    Copying 0x1500 bytes to 0x41cbac00
    Copying 0xb30 bytes to 0x41cbc100
    Setting entry point for core 4 @0x41010000
    Sciclient_procBootReleaseProcessor, ProcId 0x20...
    Sciclient_procBootReleaseProcessor, ProcId 0x21...
    Sciclient_procBootReleaseProcessor, ProcId 0x1...
    Sciclient_procBootReleaseProcessor, ProcId 0x2...
    Sciclient_procBootReleaseProcessor, ProcId 0x6...
    Sciclient_procBootReleaseProcessor, ProcId 0x7...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciserver Built On: Nov  5 2020 22:47:06
    Starting Sciserver..... PASSED
    

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    Can you read the register: 0x688040

    Check if the value is 0x80000001 as per the discussion in the thread above?
    The above is needed for correct setting.

    - Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    As shown in the above log, the value was confirmed after the register setting. The register is set correctly.

    PLL8_SS_CTRL Register Value = 0x80000001

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    Couple of things:

    1. Just make sure that PLL8_SS_CTRL Register Value = 0x80000001 is set before you set the clock frequency.
    2. Can you share the application used to test the performance?

    If you are testing A72 performance frequency decrease should have some impact. Hence the question.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    The MPU clock frequency and PLL8 settings checked in the SBL (after setting the MPU clock) and in the MPU application (in the main function) were different, 1.2GHz in the SBL, 2GHz in the MPU application. So the MPU clock frequency may have been changed by something other than SBL.

    The SBL logs:

    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    PLL8_SS_CTRL Register Value = 0x80000001
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1

    6786.SBL_log.txt
    SBL Revision: 01.00.10.00 (May 27 2021 - 13:53:44)
    TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
    SCISERVER Board Configuration header population... PASSED
    Sciclient_setBoardConfigHeader... PASSED
    Initlialzing PLLs ...done.
    InitlialzingClocks ...done.
    Initlialzing DDR ...done.
    Initializing GTC ...Begin parsing user application
    Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
    Searching for X509 certificate ...not found
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Enabling MCU TCMs after reset for core 4
    Disabling HW-based memory init of MCU TCMs for core 4
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Copying 0x40 bytes to 0x41010000
    Copying 0x2c88 bytes to 0x41010100
    Copying 0x500 bytes to 0x41015980
    Copying 0x28 bytes to 0x41015e80
    Copying 0x10 bytes to 0x41015ea8
    Copying 0x13f40 bytes to 0x41c9c320
    Copying 0x6e50 bytes to 0x41cb0260
    Copying 0x1500 bytes to 0x41cbac00
    Copying 0xb30 bytes to 0x41cbc100
    Setting entry point for core 4 @0x41010000
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x798 bytes to 0x90000800
    Copying 0x2a8 bytes to 0x90100000
    Copying 0x1c990 bytes to 0x90200000
    Copying 0x3a10 bytes to 0x9021c990
    Copying 0x23298 bytes to 0x90221000
    Setting entry point for core 0 @0x90100000
    Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x90100000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    PLL8_SS_CTRL Register Value = 0x80000001
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Sciclient_pmSetModuleState Off, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0xca...
    Sciclient_procBootReleaseProcessor, ProcId 0x20...
    Sciclient_procBootReleaseProcessor, ProcId 0x21...
    Sciclient_procBootReleaseProcessor, ProcId 0x1...
    Sciclient_procBootReleaseProcessor, ProcId 0x2...
    Sciclient_procBootReleaseProcessor, ProcId 0x6...
    Sciclient_procBootReleaseProcessor, ProcId 0x7...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciserver Built On: Nov  5 2020 22:47:06
    Starting Sciserver..... PASSED
    

    The MPU application logs:

    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x68
    FB_DIV_INT Field Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    FB_DIV_FRAC Field Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8000
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x0

    0333.app_log.txt
     Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x68
    FB_DIV_INT Field Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    FB_DIV_FRAC Field Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8000
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x0
    

    Can the MPU clock frequency be changed by SYSBIOS initialization (before main)?

    If so, in which file is the MPU clock frequency defined?

    I will suggest to our customer to try a bare metal application instead of a BIOS application.

    Best regards,

    Daisuke

  • Hi Keerthy-san,

    I have an additional question.

    Does the PLL8_SS_CTRL Register Value = 0x80000001 really need to be set?

    When the HSDIV output is used, the MPU clock frequency seems to be 600MHz instead of 1.2GHz.

    FOUTP = (FREF / REFDIV) * (FBDIV + FRAC)
                 = (FREF / REF_DIV) * (FB_DIV_INT + FB_DIV_FRAC / 2^24)
                 = (19.2MHz / 1) * (125 + 0 / 16777216)
                 = 19.2MHz * 125
                 = 2400MHz

    FOUTPOSTDIV = FOUTP / (POSTDIV1 * POSTDIV2)
                               = FOUTP / (POST_DIV1 * POST_DIV2)
                               = 2400MHz / (2 * 1)
                               = 1200MHz

    PLL8_HSDIV0 output = FOUTPOSTDIV / (HSDIV + 1)
                                        = 1200MHz / (1 + 1)
                                        = 600MHz

    Best regards,

    Daisuke

  • Hello Daisuke-San,

    What is being run after SBL?

    - Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    Our customer ran ex02_bios_multicore_echo_test after SBL.

    They will try to check the MPU clock frequency and PLL8 settings on the SBL test application (sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release).

    Best regards,

    Daisuke

  • Hi Keerthy-san,

    Our customer ran the board_diag_uart_mpu1_0_release as a bare metal application after SBL.

    The MPU clock frequency checked in the MPU application (in the main function) indicates 2GHz. So the MPU clock frequency is reconfigured to 2GHz regardless of whether SYSBIOS is used.

    The SBL logs:

    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    PLL8_SS_CTRL Register Value = 0x80000001
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1

    7206.SBL_log.txt
    SBL Revision: 01.00.10.00 (May 27 2021 - 13:53:44)
    TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
    SCISERVER Board Configuration header population... PASSED
    Sciclient_setBoardConfigHeader... PASSED
    Initlialzing PLLs ...done.
    InitlialzingClocks ...done.
    Initlialzing DDR ...done.
    Initializing GTC ...Begin parsing user application
    Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
    Searching for X509 certificate ...not found
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Enabling MCU TCMs after reset for core 4
    Disabling HW-based memory init of MCU TCMs for core 4
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Copying 0x40 bytes to 0x41010000
    Copying 0x2c88 bytes to 0x41010100
    Copying 0x500 bytes to 0x41015980
    Copying 0x28 bytes to 0x41015e80
    Copying 0x10 bytes to 0x41015ea8
    Copying 0x13f40 bytes to 0x41c9c320
    Copying 0x6e50 bytes to 0x41cb0260
    Copying 0x1500 bytes to 0x41cbac00
    Copying 0xb30 bytes to 0x41cbc100
    Setting entry point for core 4 @0x41010000
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x7a0 bytes to 0x70040000
    Copying 0xc398 bytes to 0x70092000
    Copying 0x18c bytes to 0x7009e398
    Copying 0xce0 bytes to 0x7009e528
    Copying 0x498 bytes to 0x7009f210
    Copying 0x6468 bytes to 0x7009f6a8
    Setting entry point for core 0 @0x70092558
    Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70092558...
    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    PLL8_SS_CTRL Register Value = 0x80000001
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Sciclient_pmSetModuleState Off, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0xca...
    Sciclient_procBootReleaseProcessor, ProcId 0x20...
    Sciclient_procBootReleaseProcessor, ProcId 0x21...
    Sciclient_procBootReleaseProcessor, ProcId 0x1...
    Sciclient_procBootReleaseProcessor, ProcId 0x2...
    Sciclient_procBootReleaseProcessor, ProcId 0x6...
    Sciclient_procBootReleaseProcessor, ProcId 0x7...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciserver Built On: Nov  5 2020 22:47:06
    Starting Sciserver..... PASSED
    

    The MPU application logs:

    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x68
    FB_DIV_INT Field Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    FB_DIV_FRAC Field Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8000
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x0

    5460.app_log.txt
     Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x68
    FB_DIV_INT Field Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    FB_DIV_FRAC Field Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000001
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x1
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8000
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x0
    
    *********************************************
    *                 UART Test                 *
    *********************************************
    
    Testing UART print to console at 115.2k baud rate
    Press 'y' to verify pass:
    

    Our customer will try to check the MPU clock frequency and PLL8 settings on the SBL test application (sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release).

    Best regards,

    Daisuke

  • Daisuke-san, any update on customer attempt here?  Can you please summarize the latest issue as you understand it?

  • Hello Daisuke-san,

    Do you want me to try anything from my side? Let me know if you have other questions.

    - Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    Our customer is trying to find out where the MPU clock frequency is re-set up after it is set up in the SBL. So they are trying to check the MPU clock frequency and PLL8 settings on the SBL test application (sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release). They tried to read the PLL registers using the GEL file with CCS debugger instead of UART because the SBL test application does not link the UART_stdio API by default, but the read failed.

    My post about that failure is here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1007775/dra821u-how-to-debug-with-ccs-after-booting

    Also, we have another question.

    The MPU clock frequency seems to be set to half.

    For 1.2GHz:

    FOUTP = (FREF / REFDIV) * (FBDIV + FRAC)
                 = (FREF / REF_DIV) * (FB_DIV_INT + FB_DIV_FRAC / 2^24)
                 = (19.2MHz / 1) * (125 + 0 / 16777216)
                 = 19.2MHz * 125
                 = 2400MHz

    FOUTPOSTDIV = FOUTP / (POSTDIV1 * POSTDIV2)
                               = FOUTP / (POST_DIV1 * POST_DIV2)
                               = 2400MHz / (2 * 1)
                               = 1200MHz

    PLL8_HSDIV0 output = FOUTPOSTDIV / (HSDIV + 1)
                                        = 1200MHz / (1 + 1)
                                        = 600MHz

    For 2GHz:

    FOUTP = (FREF / REFDIV) * (FBDIV + FRAC)
                 = (FREF / REF_DIV) * (FB_DIV_INT + FB_DIV_FRAC / 2^24)
                 = (19.2MHz / 1) * (104 + 2796203 / 16777216)
                 = 19.2MHz * 104.1666666865348816
                 = 2000.00000038147MHz

    FOUTPOSTDIV = FOUTP / (POSTDIV1 * POSTDIV2)
                               = FOUTP / (POST_DIV1 * POST_DIV2)
                               = 2000MHz / (2 * 1)
                               = 1000MHz

    PLL8_HSDIV0 output = FOUTPOSTDIV / (HSDIV + 1)
                                        = 1000MHz / (0 + 1)
                                        = 1000MHz

    Is my calculation for the MPU clock frequency correct?

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    I will work on the above calculations on get back to you by monday.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your support.

    How is your progress for the calculations of the MPU clock frequency?

    Our customer is investigating where the MPU clock frequency is re-set up after it is set up in the SBL.

    The MPU clock frequency remains unchanged at 1.2GHz until MCU1_0 branches from SBL to the application.

    1803.SBL_log.txt
    SBL Revision: 01.00.10.00 (Jun 15 2021 - 17:03:27)
    TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
    SCISERVER Board Configuration header population... PASSED
    Sciclient_setBoardConfigHeader... PASSED
    Initlialzing PLLs ...done.
    InitlialzingClocks ...done.
    Initlialzing DDR ...done.
    Initializing GTC ...Begin parsing user application
    Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
    Searching for X509 certificate ...not found
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Enabling MCU TCMs after reset for core 4
    Disabling HW-based memory init of MCU TCMs for core 4
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Copying 0x40 bytes to 0x41010000
    Copying 0x2c88 bytes to 0x41010100
    Copying 0x500 bytes to 0x41015980
    Copying 0x28 bytes to 0x41015e80
    Copying 0x10 bytes to 0x41015ea8
    Copying 0x13f40 bytes to 0x41c9c320
    Copying 0x6e50 bytes to 0x41cb0260
    Copying 0x1500 bytes to 0x41cbac00
    Copying 0xb30 bytes to 0x41cbc100
    Setting entry point for core 4 @0x41010000
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x688 bytes to 0x70024000
    Copying 0x44 bytes to 0x70024688
    Setting entry point for core 0 @0x70024000
    Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70024000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Sciclient_pmSetModuleState Off, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0xca...
    MPU1_0 running
    Sciclient_procBootReleaseProcessor, ProcId 0x20...
    Sciclient_procBootReleaseProcessor, ProcId 0x21...
    Sciclient_procBootReleaseProcessor, ProcId 0x1...
    Sciclient_procBootReleaseProcessor, ProcId 0x2...
    Sciclient_procBootReleaseProcessor, ProcId 0x6...
    Sciclient_procBootReleaseProcessor, ProcId 0x7...
    Booting all non-SBL cores ...done.
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    RuSciserver Built On: Nov  5 2020 22:47:06
    Starting Sciserver..... PASSED
    

    After the SBL test application (sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release) runs, the settings in the PLL registers read by the memory browser on CCS indicates 2GHz.

    I suspect that the Sciserver test application (sciserver_testapp_mcu1_0_release) running on MCU1_0 re-sets the MPU clock frequency.

    Does the Sciserver test application (sciserver_testapp_mcu1_0_release) set the MPU clock frequency?

    If so, where is the MPU clock frequency defined for the Sciserver test application?

    I will suggest to our customer to try using other examples (e.g. sciclient_firmware_boot_TestApp) for SCICLIENT application.

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    Can you share the register values of PLL8_DIV_CTRL register

    devmem2 0x688038
    /dev/mem opened.
    Memory mapped at address 0xffffa5030000.
    Read at address 0x00688038 (0xffffa5038038): 0x00000001

    am seeing a value of 0x1.

    Can you please confirm the values at your end?

    - Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    > Can you share the register values of PLL8_DIV_CTRL register

    You can find it in my previous post. The value of the PLL8_DIV_CTRL register is 0x1020001 both after running the SBL and after running the application.

    After PLL is reconfigured, the values of the PLL8_FREQ_CTRL0 register, the PLL8_FREQ_CTRL1 register and the PLL8_HSDIV_CTRL0 register have changed.

    After running the SBL:

    PLL8_FREQ_CTRL0 Register Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    PLL8_HSDIV_CTRL0 Register Value = 0x8001

    After running the application:

    PLL8_FREQ_CTRL0 Register Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    PLL8_HSDIV_CTRL0 Register Value = 0x8000

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    I discussed the findings with our hardware expert.

    Refdiv = Reference/input frequency divider (on EVMs/SVBs this is 19.2MHz because that’s what the crystal produces)

    Postdiv = output divider.

     

    Now, there are multiple outputs from the PLL. In particular, there’s the VCO output (FoutP and FoutN). This is a direct tap out from the VCO, before the Post-dividers can divide the clock. This is usually done to drive the high-speed dividers.

    The high speed dividers are very simple, output = input/(divider_value + 1) => NOTE: this is because divider_value can be set to “0” in the register, and Silicon Creations didn’t want to deal with a “divide-by-zero” issue. Take the value you want and subtract “1” from it, then program that result into the HSDIV control MMR.

    As for the A72 clock frequency, currently it’s set for 2GHz. The clock comes from an HSDIV that’s connected to the VCO output like so:

    So in your calculations: POSTDIV calculations are Don't care.

    HSDIV_CLKOUT = FOUTP / (HSDIV + 1)

    Here’s a sample table of parameters to use for 1.2GHz

    Parameter

    Value for 2GHz clock

    Value for 1.2GHz clock

    Input refdiv

    1

    1

    Integer Feedback Divider

    104

    125 (19.2 * 125 = 2400)

    Fractional Feedback Divider

    2796203

    0

    POSTDIV1

    Don’t care

    Don’t care

    POSTDIV2

    Don’t care

    Don’t care

    HSDIV value*

    0

    1

    Integer vs Fractional Mode*

    PLL in Fractional Mode

    PLL in Fractional Mode

    Hope this answers your questions.

    Best Regards,
    Keerthy

  • Hi Keerthy-san,

    Thank you for your support. I understand the calculation for the MPU clock frequency.

    Our another question still remains.

    I suspect that the Sciserver test application (sciserver_testapp_mcu1_0_release) running on MCU1_0 changes the MPU clock frequency.

    Does the Sciserver test application (sciserver_testapp_mcu1_0_release) change the MPU clock frequency?

    If so, where is the MPU clock frequency defined for the Sciserver test application?

    When running the SBL test application on all cores, the MPU clock frequency did not change after being set in the SBL.

    [SBL] tiboot3.bin
    MCU1_0:sbl_mmcsd_img_mcu1_0_release.tiimage
    [TIFS] tifs.bin
    DMSC (M3_0):tifs.bin
    [Applications] app
    All cores:sbl_baremetal_boot_test_j7200_evm_all_coresTestApp_release.appimage

    After running the SBL:

    PLL8_FREQ_CTRL0 Register Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    PLL8_HSDIV_CTRL0 Register Value = 0x8001

    SBL_log_allcores.txt
    SBL Revision: 01.00.10.00 (Jun 15 2021 - 17:03:27)
    TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
    SCISERVER Board Configuration header population... PASSED
    Sciclient_setBoardConfigHeader... PASSED
    Initlialzing PLLs ...done.
    InitlialzingClocks ...done.
    Initlialzing DDR ...done.
    Initializing GTC ...Begin parsing user application
    Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
    Searching for X509 certificate ...not found
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Enabling MCU TCMs after reset for core 4
    Disabling HW-based memory init of MCU TCMs for core 4
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Copying 0x360 bytes to 0x70010000
    Setting entry point for core 4 @0x70010000
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Sciclient_pmSetModuleState Off, DevId 0xfb...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x2...
    Enabling MCU TCMs after reset for core 5
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Setting HALT for ProcId 0x2...
    Sciclient_pmSetModuleState On, DevId 0xfb...
    Clearing core_id 5  ATCM @ 0x41400000
    Clearing core_id 5  BTCM @ 0x41410000
    Copying 0x368 bytes to 0x70012000
    Setting entry point for core 5 @0x70012000
    Switching core id 6, proc_id 0x6 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
    Sciclient_procBootSetProcessorCfg, ProcId 0x6, enabling split mode...
    Sciclient_pmSetModuleState Off, DevId 0xf5...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
    Enabling MCU TCMs after reset for core 6
    Disabling HW-based memory init of MCU TCMs for core 6
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Setting HALT for ProcId 0x6...
    Sciclient_pmSetModuleState On, DevId 0xf5...
    Clearing core_id 6  ATCM @ 0x5c00000
    Clearing core_id 6  BTCM @ 0x5c10000
    Copying 0x368 bytes to 0x70014000
    Setting entry point for core 6 @0x70014000
    Sciclient_procBootSetProcessorCfg, ProcId 0x6, EntryPoint 0x70014000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xf5 @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xf5 @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x68
    FB_DIV_INT Field Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    FB_DIV_FRAC Field Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8000
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x0
    Copying first 128 bytes from app to MCU ATCM @ 0x5c00000 for core 6
    Clearing HALT for ProcId 0x6...
    Switching core id 6, proc_id 0x6 to split mode...
    Calling Sciclient_procMCU2_0 running
    BootGetProcessorState, ProcId 0x6...
    Sciclient_procBootSetProcessorCfg, ProcId 0x6, enabling split mode...
    Sciclient_pmSetModuleState Off, DevId 0xf6...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x7...
    Enabling MCU TCMs after reset for core 7
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Setting HALT for ProcId 0x7...
    Sciclient_pmSetModuleState On, DevId 0xf6...
    Clearing core_id 7  ATCM @ 0x5d00000
    Clearing core_id 7  BTCM @ 0x5d10000
    Copying 0x368 bytes to 0x70016000
    Setting entry point for core 7 @0x70016000
    Sciclient_procBootSetProcessorCfg, ProcId 0x7, EntryPoint 0x70016000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xf6 @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xf6 @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 2000000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x68
    FB_DIV_INT Field Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    FB_DIV_FRAC Field Value = 0x2aaaab
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8000
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x0
    Copying first 128 bytes from app to MCU ATCM @ 0x5d00000 for core 7
    Clearing HALT for ProcId 0x7...
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x688 bytes to 0x70024000
    CopyinMCU2_1 running
    g 0x44 bytes to 0x70024688
    Setting entry point for core 0 @0x70024000
    Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70024000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Sciclient_pmSetModuleState Off, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0xca...
    MPU1_0 running
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x688 bytes to 0x70026000
    Copying 0x44 bytes to 0x70026688
    Setting entry point for core 1 @0x70026000
    Sciclient_procBootSetProcessorCfg, ProcId 0x21, EntryPoint 0x70026000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xcb @ 1200000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xcb @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Sciclient_pmSetModuleState Off, DevId 0xcb...
    Sciclient_pmSetModuleState On, DevId 0xcb...
    Sciclient_procMPU1_1 running
    BootReleaseProcessor, ProcId 0x20...
    Sciclient_procBootReleaseProcessor, ProcId 0x21...
    Sciclient_procBootReleaseProcessor, ProcId 0x1...
    Sciclient_procBootReleaseProcessor, ProcId 0x2...
    Sciclient_procBootReleaseProcessor, ProcId 0x6...
    Sciclient_procBootReleaseProcessor, ProcId 0x7...
    Booting all non-SBL cores ...done.
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x70010000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Sciclient_procBootSetProcessorCfg, ProcId 0x2, EntryPoint 0x70012000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfb @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfb @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Copying first 128 bytes from app to MCU ATCM @ 0x41400000 for core 5
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    RuMCU1_1 running
    MCU1_0 running
    MCU1_0 reports: All tests have passed
    

    After running the application:

    PLL8_FREQ_CTRL0 Register Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    PLL8_HSDIV_CTRL0 Register Value = 0x8001

    When running the SBL test application on the MPU and the Sciserver test application on MCU1_0, the MPU clock frequency changed after being set in the SBL.

    [SBL] tiboot3.bin
    MCU1_0:sbl_mmcsd_img_mcu1_0_release.tiimage
    [TIFS] tifs.bin
    DMSC (M3_0):tifs.bin
    [Applications] app
    MPU1_0:sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release.rprc
    MCU1_0:sciserver_testapp_mcu1_0_release.rprc

    After running the SBL:

    PLL8_FREQ_CTRL0 Register Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    PLL8_HSDIV_CTRL0 Register Value = 0x8001

    SBL_log_mpu1_0.txt
    SBL Revision: 01.00.10.00 (Jun 15 2021 - 17:03:27)
    TIFS  ver: 20.8.5--v2020.08b (Terrific Lla
    SCISERVER Board Configuration header population... PASSED
    Sciclient_setBoardConfigHeader... PASSED
    Initlialzing PLLs ...done.
    InitlialzingClocks ...done.
    Initlialzing DDR ...done.
    Initializing GTC ...Begin parsing user application
    Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
    Searching for X509 certificate ...not found
    Switching core id 4, proc_id 0x1 to split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
    Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
    Enabling MCU TCMs after reset for core 4
    Disabling HW-based memory init of MCU TCMs for core 4
    Sciclient_procBootSetProcessorCfg enabling TCMs...
    Copying 0x40 bytes to 0x41010000
    Copying 0x2c88 bytes to 0x41010100
    Copying 0x500 bytes to 0x41015980
    Copying 0x28 bytes to 0x41015e80
    Copying 0x10 bytes to 0x41015ea8
    Copying 0x13f40 bytes to 0x41c9c320
    Copying 0x6e50 bytes to 0x41cb0260
    Copying 0x1500 bytes to 0x41cbac00
    Copying 0xb30 bytes to 0x41cbc100
    Setting entry point for core 4 @0x41010000
    Sciclient_pmSetModuleState On, DevId 0x4...
    Copying 0x688 bytes to 0x70024000
    Copying 0x44 bytes to 0x70024688
    Setting entry point for core 0 @0x70024000
    Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70024000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Sciclient_pmSetModuleState Off, DevId 0xca...
    Sciclient_pmSetModuleState On, DevId 0xca...
    MPU1_0 running
    Sciclient_procBootReleaseProcessor, ProcId 0x20...
    Sciclient_procBootReleaseProcessor, ProcId 0x21...
    Sciclient_procBootReleaseProcessor, ProcId 0x1...
    Sciclient_procBootReleaseProcessor, ProcId 0x2...
    Sciclient_procBootReleaseProcessor, ProcId 0x6...
    Sciclient_procBootReleaseProcessor, ProcId 0x7...
    Booting all non-SBL cores ...done.
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000...
    Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz...
    Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz...
    CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000
    BYPASS_SW_OVRD Field Value = 0x0
    BYP_WARM_RST Field Value = 0x1
    CLK_SEL Field Value = 0x0
    PLL8_FREQ_CTRL0 Register Value = 0x7d
    FB_DIV_INT Field Value = 0x7d
    PLL8_FREQ_CTRL1 Register Value = 0x0
    FB_DIV_FRAC Field Value = 0x0
    PLL8_DIV_CTRL Register Value = 0x1020001
    POST_DIV2 Field Value = 0x1
    POST_DIV1 Field Value = 0x2
    REF_DIV Field Value = 0x1
    PLL8_SS_CTRL Register Value = 0x80000000
    BYPASS_EN Field Value = 0x1
    WV_TBLE_MAXADDR Field Value = 0x0
    RESET Field Value = 0x0
    DOWNSPREAD_EN Field Value = 0x0
    WAVE_SEL Field Value = 0x0
    PLL8_SS_SPREAD Value = 0x10001
    MOD_DIV Field Value = 0x1
    SPREAD Field Value = 0x1
    PLL8_HSDIV_CTRL0 Register Value = 0x8001
    RESET Field Value = 0x0
    CLKOUT_EN Field Value = 0x1
    SYNC_DIS Field Value = 0x0
    HSDIV Field Value = 0x1
    Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4
    Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
    Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
    Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
    RuSciserver Built On: Nov  5 2020 22:47:06
    Starting Sciserver..... PASSED
    

    After running the application:

    PLL8_FREQ_CTRL0 Register Value = 0x68
    PLL8_FREQ_CTRL1 Register Value = 0x2aaaab
    PLL8_HSDIV_CTRL0 Register Value = 0x8000

    Best regards,

    Daisuke

  • Hello Daisuke-san,

    Can you share the changes done from your side for making SBL frequency change to 1.2GHz?


    I suspect that the Sciserver test application (sciserver_testapp_mcu1_0_release) running on MCU1_0 changes the MPU clock frequency.

    sciserver_testapp_mcu1_0_release is a server application for SCI running on mcu1_0 and this only changes the MPU clock frequency
    if someone is requesting it to change the frequency. Can you confirm the exact application you are running after SBL?

    I believe it is sbl_baremetal_boot_test_j7200_evm_all_coresTestApp_release.appimage. Can you confirm?

    - Keerthy

  • Hi Keerthy-san,

    Thank you for your reply.

    We modified the SBL but did not modified the applications.

    The following header file was modified to change the initial MPU clock frequency to 1.2GHz.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/soc/k3/sbl_soc_cfg.h

    sbl_soc_cfg.h

    The following two source codes were modified to add debug codes and the workaround advised in this thread.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/board/k3/sbl_main.c

    8686.sbl_main.c
    /**
     *  \file   sbl_main.c
     *
     *  \brief  This file contain main function, call the Board Initialization
     *          functions & slave core boot-up functions in sequence.
     *
     */
    
    /*
     * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * Redistributions of source code must retain the above copyright
     * notice, this list of conditions and the following disclaimer.
     *
     * Redistributions in binary form must reproduce the above copyright
     * notice, this list of conditions and the following disclaimer in the
     * documentation and/or other materials provided with the
     * distribution.
     *
     * Neither the name of Texas Instruments Incorporated nor the names of
     * its contributors may be used to endorse or promote products derived
     * from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     */
    
     /* TI RTOS header files */
    #include "sbl_main.h"
    #include <ti/csl/cslr_gtc.h>
    
    /**********************************************************************
     ************************** Macros ************************************
     **********************************************************************/
    
    /**********************************************************************
     ************************** Internal functions ************************
     **********************************************************************/
    
    /**********************************************************************
     ************************** Global Variables **************************
     **********************************************************************/
    extern sblProfileInfo_t sblProfileLog[MAX_PROFILE_LOG_ENTRIES];
    extern uint32_t sblProfileLogIndx;
    extern uint32_t sblProfileLogOvrFlw;
    
    #pragma DATA_SECTION(sblProfileLogAddr, ".sbl_profile_info")
    volatile sblProfileInfo_t * sblProfileLogAddr;
    
    #pragma DATA_SECTION(sblProfileLogIndxAddr, ".sbl_profile_info")
    volatile uint32_t *sblProfileLogIndxAddr;
    
    #pragma DATA_SECTION(sblProfileLogOvrFlwAddr, ".sbl_profile_info")
    volatile uint32_t *sblProfileLogOvrFlwAddr;
    
    sblEntryPoint_t k3xx_evmEntry;
    #if defined(SOC_AM64X)
    const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
    {
        {
            /* Region 0 configuration: complete 32 bit address space = 4Gbits */
            .regionId         = 0U,
            .enable           = 1U,
            .baseAddr         = 0x0U,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 1U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)FALSE,
            .cachePolicy      = 0U,
            .memAttr          = 0U,
        },
        {
            /* Region 1 configuration: 64K bytes ATCM for exception vector execution */
            .regionId         = 1U,
            .enable           = 1U,
            .baseAddr         = 0x0U,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
            .memAttr          = 0U,
        },
        {
            /* Region 2 configuration: 2 MB MCMS3 RAM */
            .regionId         = 2U,
            .enable           = 1U,
            .baseAddr         = 0x70000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 3 configuration: 2 GB DDR RAM */
            .regionId         = 3U,
            .enable           = 1U,
            .baseAddr         = 0x80000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 4 configuration: 64 KB BTCM */
            .regionId         = 4U,
            .enable           = 1U,
            .baseAddr         = 0x41010000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
            .memAttr          = 0U,
        },
        {
            /* Region 5 configuration: 128 MB FSS DAT0 */
            .regionId         = 5U,
            .enable           = 1U,
            .baseAddr         = 0x60000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        }
    };
    #else
    const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
    {
        {
            /* Region 0 configuration: complete 32 bit address space = 4Gbits */
            .regionId         = 0U,
            .enable           = 1U,
            .baseAddr         = 0x0U,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 1U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)FALSE,
            .cachePolicy      = 0U,
            .memAttr          = 0U,
        },
        {
            /* Region 1 configuration: 128 bytes memory for exception vector execution */
            .regionId         = 1U,
            .enable           = 1U,
            .baseAddr         = 0x0U,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
            .memAttr          = 0U,
        },
        {
            /* Region 2 configuration: 1 MB OCMS RAM - Covers RAM sizes for multiple SoCs */
            .regionId         = 2U,
            .enable           = 1U,
            .baseAddr         = 0x41C00000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 3 configuration: 2 MB MCMS3 RAM */
            .regionId         = 3U,
            .enable           = 1U,
            .baseAddr         = 0x70000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 4 configuration: 2 GB DDR RAM */
            .regionId         = 4U,
            .enable           = 1U,
            .baseAddr         = 0x80000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 5 configuration: 64 KB BTCM */
            .regionId         = 5U,
            .enable           = 1U,
            .baseAddr         = 0x41010000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
            .memAttr          = 0U,
        },
        {
            /* Region 6 configuration: Covers first 32MB of EVM Flash (FSS DAT0) */
            .regionId         = 6U,
            .enable           = 1U,
            .baseAddr         = 0x50000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_32MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 7 configuration: Covers next 16MB of EVM Flash (FSS DAT0) */
            .regionId         = 7U,
            .enable           = 1U,
            .baseAddr         = 0x52000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_16MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 8 configuration: Covers next 8MB of EVM Flash (FSS DAT0) */
            .regionId         = 8U,
            .enable           = 1U,
            .baseAddr         = 0x53000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 9 configuration: Covers next 4MB of EVM Flash (FSS DAT0) */
            .regionId         = 9U,
            .enable           = 1U,
            .baseAddr         = 0x53800000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_4MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 10 configuration: Covers next 2MB of EVM Flash (FSS DAT0) */
            .regionId         = 10U,
            .enable           = 1U,
            .baseAddr         = 0x53C00000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_2MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 11 configuration: Covers next 1MB of EVM Flash (FSS DAT0) */
            .regionId         = 11U,
            .enable           = 1U,
            .baseAddr         = 0x53E00000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 12 configuration: Covers next 512KB of EVM Flash (FSS DAT0) */
            .regionId         = 12U,
            .enable           = 1U,
            .baseAddr         = 0x53F00000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 13 configuration: Covers next 256KB of EVM Flash (FSS DAT0) */
            .regionId         = 13U,
            .enable           = 1U,
            .baseAddr         = 0x53F80000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
        {
            /* Region 14 configuration (Non-cached for PHY tuning data): Covers last 256KB of EVM Flash (FSS DAT0) */
            .regionId         = 14U,
            .enable           = 1U,
            .baseAddr         = 0x53FC0000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_256KB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            /* OSPI PHY tuning algorithm which runs in DAC mode needs
             * cache to be disabled for this section of FSS data region.
             */
            .cacheable        = (uint32_t)FALSE,
            .cachePolicy      = 0U,
            .memAttr          = 0U,
        },
        {
            /* Region 15 configuration: 128 MB FSS DAT1 */
            .regionId         = 15U,
            .enable           = 1U,
            .baseAddr         = 0x58000000,
            .size             = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
            .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
            .exeNeverControl  = 0U,
            .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
            .shareable        = 0U,
            .cacheable        = (uint32_t)TRUE,
            .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
            .memAttr          = 0U,
        },
    };
    
    #endif
    
    #if defined(SOC_J7200)
    extern void checkMpuFrequency(void);
    #endif
    
    int main()
    {
    #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200))
        cpu_core_id_t core_id;
    #endif
        uint32_t isBuildHs;
    
        SBL_ADD_PROFILE_POINT;
    
        /* Any SoC specific Init. */
    #if defined (SBL_BUILD_HS)
        isBuildHs = TRUE;
    #else
        isBuildHs = FALSE;
    #endif
        SBL_SocEarlyInit(isBuildHs);
    
        if (SBL_LOG_LEVEL > SBL_LOG_ERR)
        {
            /* Configure UART Tx pinmux. */
            Board_uartTxPinmuxConfig();
        }
    
        SBL_ADD_PROFILE_POINT;
    
        if (SBL_LOG_LEVEL > SBL_LOG_NONE)
        {
            UART_HwAttrs uart_cfg;
    
            UART_socGetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
            /* Use UART fclk freq setup by ROM */
            uart_cfg.frequency = SBL_ROM_UART_MODULE_INPUT_CLK;
            /* Disable the UART interrupt */
            uart_cfg.enableInterrupt = FALSE;
            UART_socSetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
            /* Init UART for logging. */
            UART_stdioInit(BOARD_UART_INSTANCE);
        }
    
        SBL_ADD_PROFILE_POINT;
    
        SBL_log(SBL_LOG_MIN, "%s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);
    
        SBL_ADD_PROFILE_POINT;
    
       /* Initialize the ATCM */
        memset((void *)SBL_MCU_ATCM_BASE, 0xFF, 0x8000);
    
        /* Relocate CSL Vectors to ATCM*/
        memcpy((void *)SBL_MCU_ATCM_BASE, (void *)_resetvectors, 0x100);
    
        SBL_ADD_PROFILE_POINT;
    
        /* Setup RAT */
        SBL_RAT_Config(sblRatCfgList);
    
        SBL_ADD_PROFILE_POINT;
    
        /* Load SYSFW. */
        SBL_SciClientInit();
    
        SBL_ADD_PROFILE_POINT;
    
    #if !defined(SBL_SKIP_PINMUX_ENABLE)
        /* Board pinmux. */
    #if defined(SOC_AM64X)
        /* AM64x should not re-configure Pinmux on reset */
        uint32_t mmrResetRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY)));
    
        uint32_t mmrResetMask = CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_MAIN_RESET_REQ_PROXY_MASK
            | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_WARM_OUT_RST_PROXY_MASK
            | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MCU_WARMRST_PROXY_MASK
            | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY_MASK
            | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY_MASK
            | CSL_MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY_RST_SRC_MAIN_ESM_ERROR_PROXY_MASK;
    
        if (mmrResetRegister & mmrResetMask)
        {
            /* Do not do PinMux */
            SBL_log(SBL_LOG_MAX, "SKIPPING PINMUX ENABLE\n");
        }
        else
        {
            SBL_log(SBL_LOG_MAX, "ENABLING PINMUX\n");
            Board_init(BOARD_INIT_PINMUX_CONFIG);
        }
    #else
        Board_init(BOARD_INIT_PINMUX_CONFIG);
    #endif
    
    #endif
    
    #if !defined(SBL_SKIP_LATE_INIT)
        SBL_ADD_PROFILE_POINT;
        /* Any SoC specific Init. */
        SBL_SocLateInit();
    #endif
    
    #if defined(SBL_ENABLE_PLL) && !defined(SBL_SKIP_SYSFW_INIT)
        SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
        SBL_ADD_PROFILE_POINT;
        Board_init(SBL_PLL_INIT);
        SBL_log(SBL_LOG_MAX, "done.\n");
    #endif
    
    #if defined(SBL_ENABLE_CLOCKS) && !defined(SBL_SKIP_SYSFW_INIT)
        SBL_log(SBL_LOG_MAX, "InitlialzingClocks ...");
        SBL_ADD_PROFILE_POINT;
    #if defined(SBL_ENABLE_HLOS_BOOT)
    #if defined(SOC_J721E) || defined(SOC_J7200)
        Board_initParams_t initParams;
        Board_getInitParams(&initParams);
        initParams.mainClkGrp = BOARD_MAIN_CLOCK_GROUP1;
        initParams.mcuClkGrp  = BOARD_MCU_CLOCK_GROUP1;
        Board_setInitParams(&initParams);
    #endif
    #endif
        Board_init(SBL_CLOCK_INIT);
    
        SBL_log(SBL_LOG_MAX, "done.\n");
    #endif
    
    #if defined(SBL_ENABLE_DDR) && defined(SBL_ENABLE_PLL) && defined(SBL_ENABLE_CLOCKS)  && !defined(SBL_SKIP_SYSFW_INIT)
        SBL_log(SBL_LOG_MAX, "Initlialzing DDR ...");
        SBL_ADD_PROFILE_POINT;
        Board_init(BOARD_INIT_DDR);
        SBL_log(SBL_LOG_MAX, "done.\n");
    #endif
    
    #if !defined(SBL_USE_MCU_DOMAIN_ONLY) && !defined(SBL_ENABLE_DEV_GRP_MCU)
        /* Enable GTC */
        SBL_log(SBL_LOG_MAX, "Initializing GTC ...");
        volatile uint32_t *gtcRegister = (uint32_t *) CSL_GTC0_GTC_CFG1_BASE;
        *gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK;
    #endif
    
        SBL_log(SBL_LOG_MAX, "Begin parsing user application\n");
    
        /* Boot all non-SBL cores in multi-core app image */
        SBL_BootImage(&k3xx_evmEntry);
    
        /* Export SBL logs */
        sblProfileLogAddr = sblProfileLog;
        sblProfileLogIndxAddr = &sblProfileLogIndx;
        sblProfileLogOvrFlwAddr = &sblProfileLogOvrFlw;
    
    #if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200))
        /* For J721E/J7200 we have to manage all core boots at the end, to load mcu1_0 sciserver app */
        for (core_id = MCU2_CPU0_ID; core_id <= SBL_LAST_CORE_ID; core_id ++)
        {
            /* Try booting all MAIN domain cores except the Cortex-A cores */
            if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
                SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
        }
    
        Board_releaseResource(BOARD_RESOURCE_MODULE_CLOCK);
    
        /* Boot the HLOS on the Cortex-A cores towards the end */
        for (core_id = MPU1_CPU0_ID; core_id <= MPU1_CPU1_ID; core_id ++)
        {
            /* Try booting all cores other than the cluster running the SBL */
            if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
                SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
        }
    #endif
    
    #if defined(SOC_J7200)
        SBL_log(SBL_LOG_MAX, "Booting all non-SBL cores ...done. \n");
        SBL_ADD_PROFILE_POINT;
        checkMpuFrequency();
    #endif
    
        /* Boot the core running SBL in the end */
        if ((k3xx_evmEntry.CpuEntryPoint[MCU1_CPU1_ID] != SBL_INVALID_ENTRY_ADDR) ||
            (k3xx_evmEntry.CpuEntryPoint[MCU1_CPU0_ID] < SBL_INVALID_ENTRY_ADDR))
        {
            SBL_SlaveCoreBoot(MCU1_CPU0_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
            SBL_SlaveCoreBoot(MCU1_CPU1_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
        }
    
        /* Execute a WFI */
        asm volatile (" wfi");
    
        return 0;
    }
    

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c

    2654.sbl_slave_core_boot.c
    /**
     *  \file   sbl_slave_core_boot.c
     *
     *  \brief  This file contain functions related to slave core boot-up.
     *
     */
    
    /*
     * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * Redistributions of source code must retain the above copyright
     * notice, this list of conditions and the following disclaimer.
     *
     * Redistributions in binary form must reproduce the above copyright
     * notice, this list of conditions and the following disclaimer in the
     * documentation and/or other materials provided with the
     * distribution.
     *
     * Neither the name of Texas Instruments Incorporated nor the names of
     * its contributors may be used to endorse or promote products derived
     * from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     */
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    
     #include <stdint.h>
     #include <string.h>
     #include <ti/csl/csl_types.h>
     #include <ti/csl/cslr_device.h>
     #include <ti/csl/hw_types.h>
     #include <ti/csl/arch/csl_arch.h>
     #include <ti/drv/uart/UART_stdio.h>
    
    #include "sbl_soc.h"
    #include "sbl_log.h"
    #include "sbl_soc_cfg.h"
    #include "sbl_profile.h"
    #include "sbl_err_trap.h"
    #include "sbl_sci_client.h"
    #include "sbl_slave_core_boot.h"
    
    #if defined(BOOT_OSPI)
    #include "sbl_ospi.h"
    #endif
    
    #if defined(BOOT_MMCSD)
    #include "sbl_mmcsd.h"
    #endif
    
    #if defined(BOOT_UART)
    #include "sbl_uart.h"
    #endif
    
    #if defined(BOOT_HYPERFLASH)
    #include "sbl_hyperflash.h"
    #endif
    /* ========================================================================== */
    /*                           Macros & Typedefs                                */
    /* ========================================================================== */
    #define SBL_DISABLE_MCU_LOCKSTEP    (0)
    #define SBL_ENABLE_MCU_LOCKSTEP     (1)
    
    /* Don't forget to update parameter OPP of the AVS   */
    /* setup function in SBL_SocLateInit if the CPU freq */
    /* are changed to a higher or lower operating  point */
    static const sblSlaveCoreInfo_t sbl_slave_core_info[] =
    {
        /* MPU1_CPU0 info */
        {
        SBL_PROC_ID_MPU1_CPU0,
        SBL_DEV_ID_MPU1_CPU0,
        SBL_CLK_ID_MPU1_CPU0,
        SBL_MPU1_CPU0_FREQ_HZ,
        },
        /* MPU1_CPU1 info */
        {
        SBL_PROC_ID_MPU1_CPU1,
        SBL_DEV_ID_MPU1_CPU1,
        SBL_CLK_ID_MPU1_CPU1,
        SBL_MPU1_CPU1_FREQ_HZ,
        },
        /* MPU2_CPU0 info */
        {
        SBL_PROC_ID_MPU2_CPU0,
        SBL_DEV_ID_MPU2_CPU0,
        SBL_CLK_ID_MPU2_CPU0,
        SBL_MPU2_CPU0_FREQ_HZ,
        },
        /* MPU2_CPU1 info */
        {
        SBL_PROC_ID_MPU2_CPU1,
        SBL_DEV_ID_MPU2_CPU1,
        SBL_CLK_ID_MPU2_CPU1,
        SBL_MPU2_CPU1_FREQ_HZ,
        },
        /* MCU1_CPU0 info */
        {
        SBL_PROC_ID_MCU1_CPU0,
        SBL_DEV_ID_MCU1_CPU0,
        SBL_CLK_ID_MCU1_CPU0,
        SBL_MCU1_CPU0_FREQ_HZ,
        },
        /* MCU1_CPU1 info */
        {
        SBL_PROC_ID_MCU1_CPU1,
        SBL_DEV_ID_MCU1_CPU1,
        SBL_CLK_ID_MCU1_CPU1,
        SBL_MCU1_CPU1_FREQ_HZ,
        },
        /* MCU2_CPU0 info */
        {
        SBL_PROC_ID_MCU2_CPU0,
        SBL_DEV_ID_MCU2_CPU0,
        SBL_CLK_ID_MCU2_CPU0,
        SBL_MCU2_CPU0_FREQ_HZ,
        },
        /* MCU2_CPU1 info */
        {
        SBL_PROC_ID_MCU2_CPU1,
        SBL_DEV_ID_MCU2_CPU1,
        SBL_CLK_ID_MCU2_CPU1,
        SBL_MCU2_CPU1_FREQ_HZ,
        },
        /* MCU3_CPU0 info */
        {
        SBL_PROC_ID_MCU3_CPU0,
        SBL_DEV_ID_MCU3_CPU0,
        SBL_CLK_ID_MCU3_CPU0,
        SBL_MCU3_CPU0_FREQ_HZ,
        },
        /* MCU3_CPU1 info */
        {
        SBL_PROC_ID_MCU3_CPU1,
        SBL_DEV_ID_MCU3_CPU1,
        SBL_CLK_ID_MCU3_CPU1,
        SBL_MCU3_CPU1_FREQ_HZ,
        },
        /* DSP1_C66X info */
        {
        SBL_PROC_ID_DSP1_C66X,
        SBL_DEV_ID_DSP1_C66X,
        SBL_CLK_ID_DSP1_C66X,
        SBL_DSP1_C66X_FREQ_HZ,
        },
        /* DSP2_C66X info */
        {
        SBL_PROC_ID_DSP2_C66X,
        SBL_DEV_ID_DSP2_C66X,
        SBL_CLK_ID_DSP2_C66X,
        SBL_DSP2_C66X_FREQ_HZ,
        },
        /* DSP1_C7X info */
        {
        SBL_PROC_ID_DSP1_C7X,
        SBL_DEV_ID_DSP1_C7X,
        SBL_CLK_ID_DSP1_C7X,
        SBL_DSP1_C7X_FREQ_HZ,
        },
        /* DSP2_C7X info */
        {
        SBL_PROC_ID_DSP2_C7X,
        SBL_DEV_ID_DSP2_C7X,
        SBL_CLK_ID_DSP2_C7X,
        SBL_DSP2_C7X_FREQ_HZ,
        },
        /* M4F Core0 info*/
        {
        SBL_PROC_ID_M4F_CPU0,
        SBL_DEV_ID_M4F_CPU0,
        SBL_CLK_ID_M4F_CPU0,
        SBL_M4F_CPU0_FREQ_HZ,
        }
    };
    
    static const uint32_t SblAtcmAddr[] =
    {
    SBL_MCU_ATCM_BASE,
    SBL_MCU1_CPU1_ATCM_BASE_ADDR_SOC,
    SBL_MCU2_CPU0_ATCM_BASE_ADDR_SOC,
    SBL_MCU2_CPU1_ATCM_BASE_ADDR_SOC,
    SBL_MCU3_CPU0_ATCM_BASE_ADDR_SOC,
    SBL_MCU3_CPU1_ATCM_BASE_ADDR_SOC
    };
    
    #if !defined(SOC_AM65XX)
    static const uint32_t SblBtcmAddr[] =
    {
    SBL_MCU_BTCM_BASE,
    SBL_MCU1_CPU1_BTCM_BASE_ADDR_SOC,
    SBL_MCU2_CPU0_BTCM_BASE_ADDR_SOC,
    SBL_MCU2_CPU1_BTCM_BASE_ADDR_SOC,
    SBL_MCU3_CPU0_BTCM_BASE_ADDR_SOC,
    SBL_MCU3_CPU1_BTCM_BASE_ADDR_SOC
    };
    #endif
    /* ========================================================================== */
    /*                           Internal Functions                               */
    /* ========================================================================== */
    
    static void SBL_RequestCore(cpu_core_id_t core_id)
    {
    #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
        int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
        int32_t status = CSL_EFAIL;
    
    #if defined(SOC_AM64X)
        /* Do not touch the M4 if reset isolation is enabled */
        uint32_t mmrMagicRegister;
        mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
        if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
        {
            return;
        }
    #endif
    
        if (proc_id != 0xBAD00000)
        {
            SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootRequestProcessor, ProcId 0x%x... \n", proc_id);
    
            status = Sciclient_procBootRequestProcessor(proc_id, SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                SBL_log(SBL_LOG_ERR, "Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", proc_id);
                SblErrLoop(__FILE__, __LINE__);
            }
        }
    #endif
    
        return;
    }
    
    static void SBL_RequestAllCores(void)
    {
    #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
        cpu_core_id_t core_id;
        uint32_t num_cores = sizeof(sbl_slave_core_info)/ sizeof(sblSlaveCoreInfo_t);
    
        SBL_ADD_PROFILE_POINT;
    
        for (core_id = 0; core_id < num_cores; core_id++)
        {
            SBL_RequestCore(core_id);
        }
    
        SBL_ADD_PROFILE_POINT;
    #endif
    
        return;
    }
    
    static void SBL_ReleaseCore (cpu_core_id_t core_id, uint32_t reqFlag)
    {
    #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
        int32_t proc_id = sbl_slave_core_info[core_id].tisci_proc_id;
        int32_t status = CSL_EFAIL;
    
    #if defined(SOC_AM64X)
        /* Do not touch the M4 if reset isolation is enabled */
        uint32_t mmrMagicRegister;
        mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
        if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
        {
            return;
        }
    #endif
    
        if(proc_id != 0xBAD00000)
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...\n", proc_id);
            status = Sciclient_procBootReleaseProcessor(proc_id, reqFlag, SCICLIENT_SERVICE_WAIT_FOREVER);
    
            if (status != CSL_PASS)
            {
                SBL_log(SBL_LOG_ERR, "Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", proc_id);
                SblErrLoop(__FILE__, __LINE__);
            }
        }
    #endif
    
        return;
    }
    
    static void SBL_ReleaseAllCores(void)
    {
    #if !defined(SBL_SKIP_BRD_CFG_BOARD) && !defined(SBL_SKIP_SYSFW_INIT)
        cpu_core_id_t core_id;
        uint32_t num_cores = sizeof(sbl_slave_core_info)/sizeof(sblSlaveCoreInfo_t);
    
        SBL_ADD_PROFILE_POINT;
    
        for (core_id = 0; core_id < num_cores; core_id++)
        {
            SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
        }
    
        SBL_ADD_PROFILE_POINT;
    #endif
    
        return;
    }
    
    static void SBL_ConfigMcuLockStep(uint8_t enableLockStep, const sblSlaveCoreInfo_t *sblCoreInfoPtr)
    {
        int32_t status = CSL_EFAIL;
        struct tisci_msg_proc_get_status_resp cpuStatus;
        struct tisci_msg_proc_set_config_req  proc_set_config_req;
    
        SBL_ADD_PROFILE_POINT;
    
        SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblCoreInfoPtr->tisci_proc_id);
        status = Sciclient_procBootGetProcessorState(sblCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
        if (status != CSL_PASS)
        {
            SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
            SblErrLoop(__FILE__, __LINE__);
        }
    
        proc_set_config_req.processor_id = cpuStatus.processor_id;
        proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
        proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
        proc_set_config_req.config_flags_1_set = 0;
        proc_set_config_req.config_flags_1_clear = 0;
    
        if (enableLockStep)
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling Lockstep mode...\n", cpuStatus.processor_id);
            proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
        }
        else
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, enabling split mode...\n", cpuStatus.processor_id);
            proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
        }
    
        SBL_ADD_PROFILE_POINT;
    
        status =  Sciclient_procBootSetProcessorCfg(&proc_set_config_req,  SCICLIENT_SERVICE_WAIT_FOREVER);
        if (status != CSL_PASS)
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg lockstep...NOT DONE \n");
        }
    
        SBL_ADD_PROFILE_POINT;
    
        return;
    }
    
    int32_t SBL_BootImage(sblEntryPoint_t *pEntry)
    {
        int32_t retval = 0;
        cpu_core_id_t core_id;
    
        SBL_ADD_PROFILE_POINT;
    
        /* Initialize the entry point array to 0. */
        for (core_id = MPU1_CPU0_ID; core_id < NUM_CORES; core_id ++)
            pEntry->CpuEntryPoint[core_id] = SBL_INVALID_ENTRY_ADDR;
    
        /* Request SYSW for control of all cores */
        SBL_RequestAllCores();
    
        SBL_ADD_PROFILE_POINT;
    
    #if defined(BOOT_MMCSD)
        /* MMCSD Boot Mode Image Copy function. */
        if (SBL_MMCBootImage(pEntry) != E_PASS)
    #elif defined(BOOT_OSPI)
        if (SBL_OSPIBootImage(pEntry) != E_PASS)
    #elif defined(BOOT_UART)
        if (SBL_UARTBootImage(pEntry) != E_PASS)
    #elif defined(BOOT_HYPERFLASH)
        if (SBL_HYPERFLASHBootImage(pEntry) != E_PASS)
    #endif
        {
            retval = E_FAIL;
        }
    
        SBL_ADD_PROFILE_POINT;
    
        /* Release control of all cores */
        SBL_ReleaseAllCores();
    
        SBL_ADD_PROFILE_POINT;
    
        return retval;
    }
    
    /**
     * \brief        SBL_SetupCoreMem function sets up the CPUs internal memory
     *
     * \param[in]    core_id - CPU ID
     * \param[in]    pAppEntry - Core info struct
     *
     * \return   none
     */
    void SBL_SetupCoreMem(uint32_t core_id)
    {
        int32_t status = CSL_EFAIL;
        uint8_t runLockStep = 0;
        uint8_t mcuModeConfigured = 0;
        struct tisci_msg_proc_get_status_resp cpuStatus;
        struct tisci_msg_proc_set_config_req  proc_set_config_req;
        const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr;
    
        SBL_ADD_PROFILE_POINT;
    
    #if defined(SOC_AM64X)
        /* Do not touch the M4 if reset isolation is enabled */
        uint32_t mmrMagicRegister;
        mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
        if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
        {
            return;
        }
    #endif
    
        /* Remap virtual core-ids if needed */
        switch (core_id)
        {
            case MCU1_SMP_ID:
                runLockStep = 1;
                core_id = MCU1_CPU0_ID;
                break;
            case MCU2_SMP_ID:
                runLockStep = 1;
                core_id = MCU2_CPU0_ID;
                break;
            case MCU3_SMP_ID:
                runLockStep = 1;
                core_id = MCU3_CPU0_ID;
                break;
            default:
                break;
        }
    
        sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
    
        if(runLockStep)
        {
            SBL_log(SBL_LOG_MAX, "Detected lockstep for core_id %d, proc_id 0x%x... \n", core_id, sblSlaveCoreInfoPtr->tisci_proc_id);
            SBL_ConfigMcuLockStep(SBL_ENABLE_MCU_LOCKSTEP, sblSlaveCoreInfoPtr);
            mcuModeConfigured = 1;
        }
    
        switch (core_id)
        {
    
            case DSP1_C66X_ID:
                break;
            case DSP2_C66X_ID:
                break;
            case DSP1_C7X_ID:
                break;
            case DSP2_C7X_ID:
                break;
    
            case MCU1_CPU1_ID:
            case MCU2_CPU1_ID:
            case MCU3_CPU1_ID:
                SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id-1, sbl_slave_core_info[core_id-1].tisci_proc_id);
                /* Image for second MCU core present, disable lock step for the cluster */
                SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id-1]));
                mcuModeConfigured = 1;
                /* DOnt break, fall through for enabling TCMs */
            case MCU1_CPU0_ID:
            case MCU2_CPU0_ID:
            case MCU3_CPU0_ID:
                if (!mcuModeConfigured)
                {
                    SBL_log(SBL_LOG_MAX, "Switching core id %d, proc_id 0x%x to split mode... \n", core_id, sbl_slave_core_info[core_id].tisci_proc_id);
                    /* Non-SMP image used, disable lock step for the cluster */
                    SBL_ConfigMcuLockStep(SBL_DISABLE_MCU_LOCKSTEP, &(sbl_slave_core_info[core_id]));
                }
    
                /* Ensure Power is OFF for each core before configuring TCMs */
                /* SBL running on MCU0, don't fool around with its power */
                if (core_id != MCU1_CPU0_ID)
                {
                    if (runLockStep)
                    {
                        SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
                        Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                    }
                    SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                    Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
    
                SBL_log(SBL_LOG_MAX, "Calling Sciclient_procBootGetProcessorState, ProcId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_proc_id);
                status = Sciclient_procBootGetProcessorState(sblSlaveCoreInfoPtr->tisci_proc_id, &cpuStatus, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_procBootGetProcessorState...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
    
                proc_set_config_req.processor_id = cpuStatus.processor_id;
                proc_set_config_req.bootvector_lo = cpuStatus.bootvector_lo;
                proc_set_config_req.bootvector_hi = cpuStatus.bootvector_hi;
                proc_set_config_req.config_flags_1_set = 0;
                proc_set_config_req.config_flags_1_clear = 0;
    #if defined(SOC_AM65XX)
                SBL_log(SBL_LOG_MAX, "Restore TCM defaults (ATCM disabled), after reset, for core %d\n", core_id);
                proc_set_config_req.config_flags_1_clear |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
    #else
                SBL_log(SBL_LOG_MAX, "Enabling MCU TCMs after reset for core %d\n", core_id);
                proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
    #endif
                proc_set_config_req.config_flags_1_set |= (TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN |
                                                           TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE);
    
    #if defined(SOC_J7200) || defined(SOC_AM64X)
                /* Only need to set mem_init disable bit for MCU1_0 or MCU2_0 (for each cluster) */
                if ((core_id == MCU1_CPU0_ID) || (core_id == MCU2_CPU0_ID))
                {
                    SBL_log(SBL_LOG_MAX, "Disabling HW-based memory init of MCU TCMs for core %d\n", core_id);
                    proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS;
                }
    #endif
    
                SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
                status =  Sciclient_procBootSetProcessorCfg(&proc_set_config_req,  SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
    
    #if !defined(SOC_AM65XX)
                /* Only initialize TCMs for Non-AM65xx SoCs. For AM65xx, TCMs must be initialized by the app itself. */
    
                /* For lockstep R5 pairs, this section will naturally only set HALT bit for MCU2_CPU0_ID or MCU3_CPU0_ID */
                if (core_id != MCU1_CPU0_ID)
                {
                    SBL_log(SBL_LOG_MAX, "Setting HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
                    status =  Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                    if (status != CSL_PASS)
                    {
                        SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
                        SblErrLoop(__FILE__, __LINE__);
                    }
                }
    
                /* SBL running on MCU0, don't fool around with its power & TCMs */
                if (core_id != MCU1_CPU0_ID)
                {
                    if (runLockStep)
                    {
                        /* If in lock-step mode, need to bring Core 1 out of reset, before Core 0, in order to init TCMs */
                        SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id + 1);
                        Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id + 1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                    }
                    SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                    Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
    
                    /* Initialize the TCMs - TCMs of MCU running SBL are already initialized by ROM & SBL */
    #if defined(SOC_J7200)
                    /* J7200: ATCM in lock-step is the combined size of both the split-mode ATCMs */
                    if (runLockStep)
                    {
                        SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
                        memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
                    }
                    else
                    /* Clear the normal size of ATCM for non-lockstep cores */
    #endif
                    {
                        SBL_log(SBL_LOG_MAX, "Clearing core_id %d  ATCM @ 0x%x\n", core_id, SblAtcmAddr[core_id - MCU1_CPU0_ID]);
                        memset(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
                    }
    
    #ifndef VLAB_SIM
    #if defined(SOC_J7200)
                    /* J7200: BTCM in lock-step is the combined size of both the split-mode BTCMs */
                    if (runLockStep)
                    {
                        SBL_log(SBL_LOG_MAX, "Clearing core_id %d (lock-step) BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
                        memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x10000);
                    }
                    else
                    /* Clear the normal size of BTCM for non-lockstep cores */
    #endif
                    {
                        SBL_log(SBL_LOG_MAX, "Clearing core_id %d  BTCM @ 0x%x\n", core_id, SblBtcmAddr[core_id - MCU1_CPU0_ID]);
                        memset(((void *)(SblBtcmAddr[core_id - MCU1_CPU0_ID])), 0xFF, 0x8000);
                    }
    #else
    /* BTCM is not recognized in VLAB : ASTC TICKET # TBD */
                    SBL_log(SBL_LOG_MAX, "***Not Clearing*** BTCM @0x%x\n", SblBtcmAddr[core_id - MCU1_CPU0_ID]);
    #endif
                }
    #endif /* #if !defined(SOC_AM65XX) */
                break;
            case MPU1_SMP_ID:
            case MPU1_CPU0_ID:
            case MPU1_CPU1_ID:
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
                Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                break;
            case MPU2_SMP_ID:
            case MPU2_CPU0_ID:
            case MPU2_CPU1_ID:
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
                Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                break;
            case M4F_CPU0_ID:
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState Off...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
                SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, DevId 0x%x with RESET \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 1, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RESET ...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
    
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                status = Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleState...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
                break;
            case MPU_SMP_ID:
                /* Enable SMP on all MPU clusters. Enable SMP only if cluster is present */
                if (SBL_DEV_ID_MPU_CLUSTER0 != 0xBAD00000)
                {
                    SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER0);
                    Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
                if (SBL_DEV_ID_MPU_CLUSTER1 != 0xBAD00000)
                {
                    SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", SBL_DEV_ID_MPU_CLUSTER1);
                    Sciclient_pmSetModuleState(SBL_DEV_ID_MPU_CLUSTER1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
                break;
            default:
                /* No special memory setup needed */
                break;
        }
    
        SBL_ADD_PROFILE_POINT;
    
        return;
    }
    
    #if defined(SOC_J7200)
    void checkMpuFrequency(void)
    {
        int32_t cslRet = CSL_EFAIL;
        int32_t tisci_dev_id = TISCI_DEV_A72SS0_CORE0_0;
        int32_t tisci_clk_id = TISCI_DEV_A72SS0_CORE0_0_ARM_CLK_CLK;
        uint64_t currentFreq;
        uint32_t regRdVal;
    
        cslRet = Sciclient_pmGetModuleClkFreq(tisci_dev_id,
                                              tisci_clk_id,
                                              &currentFreq,
                                              SCICLIENT_SERVICE_WAIT_FOREVER);
        if (cslRet != CSL_PASS)
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_pmGetModuleClkFreq...FAILED \n");
        }
        else
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_pmGetModuleClkFreq, DevId 0x%x @ %dHz... \n", tisci_dev_id, currentFreq);
        }
        SBL_ADD_PROFILE_POINT;
    
        regRdVal = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL);
        SBL_log(SBL_LOG_MAX, "CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "BYPASS_SW_OVRD Field Value = 0x%x \n", CSL_FEXT(regRdVal, WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD));
        SBL_log(SBL_LOG_MAX, "BYP_WARM_RST Field Value = 0x%x \n", CSL_FEXT(regRdVal, WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_BYP_WARM_RST));
        SBL_log(SBL_LOG_MAX, "CLK_SEL Field Value = 0x%x \n", CSL_FEXT(regRdVal, WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_CLK_SEL));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL0);
        SBL_log(SBL_LOG_MAX, "PLL8_FREQ_CTRL0 Register Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "FB_DIV_INT Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL0_FB_DIV_INT));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL1);
        SBL_log(SBL_LOG_MAX, "PLL8_FREQ_CTRL1 Register Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "FB_DIV_FRAC Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL1_FB_DIV_FRAC));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL);
        SBL_log(SBL_LOG_MAX, "PLL8_DIV_CTRL Register Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "POST_DIV2 Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL_POST_DIV2));
        SBL_log(SBL_LOG_MAX, "POST_DIV1 Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL_POST_DIV1));
        SBL_log(SBL_LOG_MAX, "REF_DIV Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL_REF_DIV));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL);
        SBL_log(SBL_LOG_MAX, "PLL8_SS_CTRL Register Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "BYPASS_EN Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_BYPASS_EN));
        SBL_log(SBL_LOG_MAX, "WV_TBLE_MAXADDR Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_WV_TBLE_MAXADDR));
        SBL_log(SBL_LOG_MAX, "RESET Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_RESET));
        SBL_log(SBL_LOG_MAX, "DOWNSPREAD_EN Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_DOWNSPREAD_EN));
        SBL_log(SBL_LOG_MAX, "WAVE_SEL Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_WAVE_SEL));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD);
        SBL_log(SBL_LOG_MAX, "PLL8_SS_SPREAD Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "MOD_DIV Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD_MOD_DIV));
        SBL_log(SBL_LOG_MAX, "SPREAD Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD_SPREAD));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0);
        SBL_log(SBL_LOG_MAX, "PLL8_HSDIV_CTRL0 Register Value = 0x%x \n", regRdVal);
        SBL_log(SBL_LOG_MAX, "RESET Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_RESET));
        SBL_log(SBL_LOG_MAX, "CLKOUT_EN Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_CLKOUT_EN));
        SBL_log(SBL_LOG_MAX, "SYNC_DIS Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_SYNC_DIS));
        SBL_log(SBL_LOG_MAX, "HSDIV Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_HSDIV));
    
        SBL_ADD_PROFILE_POINT;
    }
    #endif
    
    /**
     * \brief    SBL_SlaveCoreBoot function sets the entry point, sets up clocks
     *           and enable to core to start executing from entry point.
     *
     * \param    core_id = Selects a core on the SOC, refer to cpu_core_id_t enum
     *           freqHz = Speed of core at boot up, 0 indicates use SBL default freqs.
     *           pAppEntry = SBL entry point struct
     *           requestCoresFlag = Specify whether cores should be requested/released
     *               from within SBL_SlaveCoreBoot. Accepts the values SBL_REQUEST_CORE
     *               and SBL_DONT_REQUEST_CORE.
     *
     **/
    void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *pAppEntry, uint32_t requestCoresFlag)
    {
        int32_t status = CSL_EFAIL;
        struct tisci_msg_proc_set_config_req  proc_set_config_req;
        const sblSlaveCoreInfo_t *sblSlaveCoreInfoPtr = &(sbl_slave_core_info[core_id]);
        uint64_t respFreq, currentFreq;
    
        SBL_ADD_PROFILE_POINT;
    
    #if defined(SOC_AM64X)
        /* Do not touch the M4 if reset isolation is enabled */
        uint32_t mmrMagicRegister;
        mmrMagicRegister = (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD)));
        if (core_id == M4F_CPU0_ID && mmrMagicRegister != 0)
        {
            return;
        }
    #endif
    
    #if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
        /* Skip copy if R5 app entry point is already 0 */
    #if !defined(SOC_AM65XX)  /* Pre-loading ATCM is not permitted for AM65xx */
        if ((core_id == MCU1_CPU0_ID) &&
           (pAppEntry->CpuEntryPoint[core_id]) &&
           (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR))
        {
            SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
            memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
            return;
        }
    #endif
    
        /* Finished processing images for all cores, start MCU_0 */
        if ((core_id == MCU1_CPU1_ID) &&
            (pAppEntry->CpuEntryPoint[core_id] >=  SBL_INVALID_ENTRY_ADDR))
        {
                /* Display profile logs */
                SBL_printProfileLog();
    
                SBL_log(SBL_LOG_MAX, "Starting app, branching to 0x0 \n");
                /* Branch to start of ATCM */
                ((void(*)(void))0x0)();
        }
    #endif
    
        /* Request core */
        if (requestCoresFlag == SBL_REQUEST_CORE)
        {
            SBL_RequestCore(core_id);
        }
    
        /* Set entry point as boot vector */
        proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
        proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
        proc_set_config_req.bootvector_hi = 0x0;
        proc_set_config_req.config_flags_1_set = 0;
        proc_set_config_req.config_flags_1_clear = 0;
    
        if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
        {
            SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg, ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
            SBL_ADD_PROFILE_POINT;
            status =  Sciclient_procBootSetProcessorCfg(&proc_set_config_req,  SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetProcessorCfg...FAILED \n");
                SblErrLoop(__FILE__, __LINE__);
            }
    
            status = Sciclient_pmQueryModuleClkFreq (sblSlaveCoreInfoPtr->tisci_dev_id,
                                                     sblSlaveCoreInfoPtr->tisci_clk_id,
                                                     sblSlaveCoreInfoPtr->slave_clk_freq_hz,
                                                     &respFreq,
                                                     SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                SBL_log(SBL_LOG_MAX, "Sciclient_pmQueryModuleClkFreq...FAILED \n");
                SblErrLoop(__FILE__, __LINE__);
            }
            else
            {
                SBL_log(SBL_LOG_MAX, "Sciclient_pmQueryModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, respFreq);
            }
            SBL_ADD_PROFILE_POINT;
    
    #if defined(SOC_J7200)
            if (core_id == MPU1_CPU0_ID)
            {
                /* PLL8_HSDIV0 output is selected and output to MAIN_PLL8_HSDIV0_CLKOUT */
                CSL_REG32_FINS(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_WAVE_SEL, 0x1);
                SBL_log(SBL_LOG_MAX, "PLL8_SS_CTRL Register Value = 0x%x \n", CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL));
    
                /* OBSCLK0_MUX1_CLKOUT = MAIN_PLL8_HSDIV0_CLKOUT / DIV8 */
                CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK1_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK1_CTRL_CLK_SEL, 0x1);
                SBL_log(SBL_LOG_MAX, "CTRLMMR_OBSCLK1_CTRL Register Value = 0x%x \n", CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK1_CTRL));
    
                /* OBSCLK0_MUX0_CLKOUT = OBSCLK0_MUX1_CLKOUT. The clock is divided and output to the OBSCLK[2:0] pins */
                CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_SEL, 0xD);
    
                /* OBSCLK0 output clock is divided by 2 (clkdiv = 1). The maximum supported frequency is 200 MHz */
                CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_DIV, 0x1);
    
                /* Load the new divider value */
                CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_DIV_LD, 0x0);
                CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_DIV_LD, 0x1);
    
                SBL_log(SBL_LOG_MAX, "CTRLMMR_OBSCLK0_CTRL Register Value = 0x%x \n", CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL));
    
                SBL_ADD_PROFILE_POINT;
            }
    #endif
    
            SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, sblSlaveCoreInfoPtr->slave_clk_freq_hz);
            SBL_ADD_PROFILE_POINT;
            status = Sciclient_pmSetModuleClkFreq(sblSlaveCoreInfoPtr->tisci_dev_id,
                                                  sblSlaveCoreInfoPtr->tisci_clk_id,
                                                  sblSlaveCoreInfoPtr->slave_clk_freq_hz,
                                                  TISCI_MSG_FLAG_AOP,
                                                  SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq...FAILED \n");
                SblErrLoop(__FILE__, __LINE__);
            }
            SBL_ADD_PROFILE_POINT;
    
    #if defined(SOC_J7200)
            if (core_id == MPU1_CPU0_ID)
            {
                checkMpuFrequency();
            }
            else
            {
    #endif
    
            status = Sciclient_pmGetModuleClkFreq(
                                    sblSlaveCoreInfoPtr->tisci_dev_id,
                                    sblSlaveCoreInfoPtr->tisci_clk_id,
                                    &currentFreq,
                                    SCICLIENT_SERVICE_WAIT_FOREVER);
            if (status != CSL_PASS)
            {
                SBL_log(SBL_LOG_MAX, "Sciclient_pmGetModuleClkFreq...FAILED \n");
                SblErrLoop(__FILE__, __LINE__);
            }
            else
            {
                SBL_log(SBL_LOG_MAX, "Sciclient_pmGetModuleClkFreq, DevId 0x%x @ %dHz... \n", sblSlaveCoreInfoPtr->tisci_dev_id, currentFreq);
            }
            SBL_ADD_PROFILE_POINT;
    
    #if defined(SOC_J7200)
            }
    #endif
        }
        else
        {
            SBL_log(SBL_LOG_MAX, "Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x%x, EntryPoint 0x%x...\n", proc_set_config_req.processor_id, proc_set_config_req.bootvector_lo);
        }
        /* Power down and then power up each core*/
        switch (core_id)
        {
            case MCU1_CPU1_ID:
                /* Display profile logs */
                SBL_printProfileLog();
    
    #if !defined(SOC_AM65XX)  /* Pre-loading ATCM is not permitted for AM65xx */
                if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
                {
                    /* Skip copy if R5 app entry point is already 0 */
                    if (pAppEntry->CpuEntryPoint[core_id])
                    {
                        SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
                        memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
                    }
                }
    #endif
    
    #ifdef SBL_SKIP_MCU_RESET
                if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
                {
    #if !defined(SOC_AM65XX)
                    /* Un-halt MCU1_1 core */
                    Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                    Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
    #endif
                    Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
      
                /* Release the CPU and branch to app */
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
                }
    
    #if defined(SOC_J7200)
                SBL_log(SBL_LOG_MAX, "Running SBL ...done. \n");
                SBL_ADD_PROFILE_POINT;
                checkMpuFrequency();
                SBL_log(SBL_LOG_MAX, "SBL will branch to start of MCU1_0 application without resetting the core. \n");
                SBL_ADD_PROFILE_POINT;
    #endif
    
                /* Start the App - Branch to start of ATCM (0x0) */
                ((void(*)(void))0x0)();
    #else
                /* Request MCU1_0 */
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    SBL_RequestCore(core_id - 1);
                }
    
                /** 
                 * Reset sequence for cluster running SBL
                 *
                 *   The reset sequence for the cluster running SBL has to be done differently from
                 *   that of other clusters. More detail is described in comments below, but a high-
                 *   level overview of the reset sequence is as follows:
                 *
                 *   1. Processor Boot Wait (holds the queue)
                 *   2. MCU1_1 Enter Reset - (AM65x case: already powered OFF)
                 *   3. MCU1_0 Enter Reset - (AM65x case: Power OFF)
                 *   4. Un-halt MCU1_1     - (AM65x case: Not necessary)
                 *   5. Release control of MCU1_0
                 *   6. Release control of MCU1_1
                 *   7. MCU1_0 Leave Reset - (AM65x case: Power ON)
                 *   8. MCU1_1 Leave Reset (if an application is requested to run there) - (AM65x case: Power ON)
                 */
    
                /**
                 * Processor Boot Wait
                 *
                 *   DMSC will block until a WFI is issued, thus allowing the following commands
                 *   to be queued so this cluster may be reset by DMSC (queue length is defined in 
                 *   "drv/sciclient/soc/sysfw/include/<soc>/tisci_sec_proxy.h"). If these commands
                 *   were to be issued and executed prior to WFI, the cluster would enter reset and
                 *   SBL would quite sensibly not be able to tell DMSC to take itself out of reset.
                 */
                /* SBL_log(SBL_LOG_MAX, "Sciclient_procBootWaitProcessorState, ProcId 0x%x... \n", SBL_PROC_ID_MCU1_CPU0); */
                status = Sciclient_procBootWaitProcessorState(SBL_PROC_ID_MCU1_CPU0, 1, 1, 0, 3, 0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_procBootWaitProcessorState...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
    
                /**
                 * Both cores enter reset
                 *
                 *   It is necessary to reset MCU1_1 before MCU1_0, so as to maintain the specification that
                 *   MCU1_1 may never ben in a higher functional state than MCU1_0.
                 */
    #if !defined(SOC_AM65XX)
                Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
    
                /**
                 * Un-halt MCU1_1 (MCU1_0 is not halted)
                 */
                Sciclient_procBootSetSequenceCtrl(SBL_PROC_ID_MCU1_CPU1, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
    #else
                /* AM65x case (can't use local reset flags): Power down core running SBL */
                Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
    #endif
    
                /**
                 * Notify SYSFW that the SBL is relinquishing the MCU cluster running the SBL
                 */
    #if !defined(SOC_J721E) && !defined(SOC_J7200)
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                    Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
    #endif
                /**
                 * MCU1_0 and (optionally) MCU1_1 leave reset
                 *
                 *   Ensuring that MCU1_1 is never in a higher functional state than MCU1_0, both cores
                 *   shall leave reset. Only take MCU1_1 out of reset if an application will be running
                 *   on it.
                 */
    #if !defined(SOC_AM65XX)
                Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU0, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
                {
                    Sciclient_pmSetModuleRst_flags(SBL_DEV_ID_MCU1_CPU1, 0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
    #else
                /* AM65x case (can't use local reset flags): Power ON CPU0 core, then power ON CPU1 core if necessary */
                Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU0, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
                {
                    Sciclient_pmSetModuleState(SBL_DEV_ID_MCU1_CPU1, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
    #endif
    
    #if defined(SOC_J721E) || defined(SOC_J7200)
                /* Notifying SYSFW that the SBL is relinquishing the MCU cluster running the SBL */
                /* This is done at the end as the PM set module state relies on the fact the SBL is the owner of MCU1_0 and MCU1_1 */
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU0, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                    Sciclient_procBootReleaseProcessor(SBL_PROC_ID_MCU1_CPU1, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                }
    #endif
    
    #if defined(SOC_J7200)
                SBL_log(SBL_LOG_MAX, "Running SBL ...done. \n");
                SBL_ADD_PROFILE_POINT;
                checkMpuFrequency();
                SBL_log(SBL_LOG_MAX, "SBL will wait for reset to run MCU1_0 application. \n");
                SBL_ADD_PROFILE_POINT;
    #endif
    
                /* Execute a WFI */
                asm volatile ("    wfi");
    #endif
                break;
    
            case MCU1_CPU0_ID:
                /* Skip copy if R5 app entry point is already 0 */
    #if !defined(SOC_AM65XX)  /* Pre-loading ATCM is not permitted for AM65xx */
                if (pAppEntry->CpuEntryPoint[core_id])
                {
                    SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
                    memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
                }
    #endif
                break;
            case MCU2_CPU0_ID:
            case MCU2_CPU1_ID:
            case MCU3_CPU0_ID:
            case MCU3_CPU1_ID:
                if (pAppEntry->CpuEntryPoint[core_id] <  SBL_INVALID_ENTRY_ADDR)
                {
                    /* Skip copy if R5 app entry point is already 0 */
                    if (pAppEntry->CpuEntryPoint[core_id])
                    {
                        SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
                        memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(proc_set_config_req.bootvector_lo), 128);
                    }
                    SBL_log(SBL_LOG_MAX, "Clearing HALT for ProcId 0x%x...\n", sblSlaveCoreInfoPtr->tisci_proc_id);
                    status =  Sciclient_procBootSetSequenceCtrl(sblSlaveCoreInfoPtr->tisci_proc_id, 0, TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                    if (status != CSL_PASS)
                    {
                        SBL_log(SBL_LOG_ERR, "Sciclient_procBootSetSequenceCtrl...FAILED \n");
                        SblErrLoop(__FILE__, __LINE__);
                    }
                }
    
                /* Release core */
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
                }
    
                SBL_ADD_PROFILE_POINT;
                break;
           case M4F_CPU0_ID:
                SBL_log(SBL_LOG_MAX, "Calling Sciclient_pmSetModuleRst, ProcId 0x%x with RELEASE \n", sblSlaveCoreInfoPtr->tisci_proc_id);
                status = Sciclient_pmSetModuleRst(sblSlaveCoreInfoPtr->tisci_dev_id, 0, SCICLIENT_SERVICE_WAIT_FOREVER);
                if (status != CSL_PASS)
                {
                    SBL_log(SBL_LOG_ERR, "Sciclient_pmSetModuleRst RELEASE...FAILED \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
    
                /* Release core */
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
                }
    
                SBL_ADD_PROFILE_POINT;
                break;
            default:
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState Off, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
                SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleState On, DevId 0x%x... \n", sblSlaveCoreInfoPtr->tisci_dev_id);
                Sciclient_pmSetModuleState(sblSlaveCoreInfoPtr->tisci_dev_id, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
    
                /* Release core */
                if (requestCoresFlag == SBL_REQUEST_CORE)
                {
                    SBL_ReleaseCore(core_id, TISCI_MSG_FLAG_AOP);
                }
    
                SBL_ADD_PROFILE_POINT;
                break;
        }
    }
    

    The following application image was used to run the SBL test application on all cores.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/example/k3MulticoreApp/binary/j7200/sbl_baremetal_boot_test_j7200_evm_all_coresTestApp_release.appimage

    The following application images were used to run the SBL test application on the MPU and the Sciserver test application on MCU1_0.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/example/k3MulticoreApp/binary/j7200/sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release.rprc

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/binary/sciserver_testapp/bin/j7200/sciserver_testapp_mcu1_0_release.rprc

    The following firmware images were used to run the SBL on the MCU1_0 and the TIFS system firmware on DMSC (M3_0).

    ~ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/binary/j7200_evm/mmcsd/bin/sbl_mmcsd_img_mcu1_0_release.tiimage

    ~ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/drv/sciclient/soc/V2/tifs.bin

    The SBL and the SBL test applications were built with the following commands.

    cd ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/build
    make clean all

    The Sciserver test application was built with the following commands.

    cd ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/build
    make -s sciserver_testapp_clean BOARD=j7200_evm CORE=mcu1_0
    make -s sciserver_testapp BOARD=j7200_evm CORE=mcu1_0

    The multicore image was generated with the following command.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen LE 55 output.appimage 0 sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release.rprc 4 sciserver_testapp_mcu1_0_release.rprc

    Best regards,

    Daisuke

  • Hi Keerthy-san,

    I checked the source codes of the SBL test application.

    ~ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/example/k3MulticoreApp/
      /sbl_multicore_a53.asm
      /sbl_multicore_r5.asm
      /sbl_amp_multicore.c

    The MPU clock frequency does not seem to be set in the SBL test application.

    On the other hand, the Sciserver test application (sciserver_testapp_mcu1_0_release) runs on MCU1_0 with TI-RTOS.

    Is the MPU clock frequency set with the initialization by TI-RTOS?

    If so, where is the MPU clock frequency defined for the TI-RTOS initialization?

    Best regards,

    Daisuke

  • Hi Keerthy-san,

    I'm sorry to post many times.

    The System firmware sets the PLL as the default during boot.

    J7200 PLL Defaults
    software-dl.ti.com/.../pll_data.html

    Does the System firmware on the DMSC (M3_0) change the PLL8 (the MPU clock frequency) to the default after the SBL on the MCU1_0 sets it?

    Our customer has been unable to change the MPU clock frequency for 2 months.

    Should we change the MPU clock frequency by Sciclient_pmSetModuleClkFreq() in an MPU application instead of the SBL?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • Hi Keerthy-san,

    My understanding is incorrect in my previous post.

    > Does the System firmware on the DMSC (M3_0) change the PLL8 (the MPU clock frequency) to the default after the SBL on the MCU1_0 sets it?

    For the DRA821, the RM/PM SCI server part in the system firmware runs on the MCU R5 instead of the DMSC (M3_0).

    software-dl.ti.com/.../TISCI.html

    If the RM/PM SCI server runs with the Sciserver test application (sciserver_testapp_mcu1_0_release) on MCU1_0 and sets the PLL to the default during boot, it will change the MPU clock frequency to the default (2GHz) after running SBL.

    software-dl.ti.com/.../pll_data.html

    Is my understanding correct?

    Should we change the MPU clock frequency by Sciclient_pmSetModuleClkFreq() in an MPU application instead of the SBL?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • Hi Daisuke-san,

    I am looking through the thread for the context but meanwhile based on your last post:

    For the DRA821, the RM/PM SCI server part in the system firmware runs on the MCU R5 instead of the DMSC (M3_0).

    This is correct. The RM/PM collectively called DM (Device Manager) runs on the MCU1_0 and caters to requests from the non-secure cores.

    When you do an SciClient init, this will use the default RM and PM configuration and will reset the PLLs to default based on http://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/pll_data.html 

    Can you try changing the frequency after this point in the MCU app and see if things are working as expected?

    Regards,

    Karan

  • Hi Karan-san,

    Thank you for your reply.

    > Can you try changing the frequency after this point in the MCU app and see if things are working as expected?

    Can the MPU clock frequency be changed by Sciclient_pmSetModuleClkFreq() in the Sciserver test application (sciserver_testapp_mcu1_0_release) on MCU1_0?

    If so, the following source code will be modified.

    ~ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/drv/sciclient/examples/sciserver_testapp/sciserver_testapp_main.c

    Best regards,

    Daisuke

  • Hi Karan-san,

    The MPU clock frequency was changed in the Sciserver test application (sciserver_testapp_mcu1_0_release) and also remained the same in a MPU application.

    The following source code was modified to change the MPU clock frequency to 1.2GHz in the Sciserver test application (sciserver_testapp_mcu1_0_release).

    ~ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/drv/sciclient/examples/sciserver_testapp/sciserver_testapp_main.c

    3113.sciserver_testapp_main.c
    /*
     *  Copyright (C) 2020 Texas Instruments Incorporated
     *
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     *  modification, are permitted provided that the following conditions
     *  are met:
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     *    notice, this list of conditions and the following disclaimer.
     *
     *    Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the
     *    distribution.
     *
     *    Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     */
    
    /**
     *  \file sciserver_testapp_main.c
     *
     *  \brief Example Application for sciserver
     *
     */
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    
    #include <ti/sysbios/BIOS.h>
    #include <ti/board/board.h>
    #include <ti/drv/sciclient/sciserver_tirtos.h>
    #include <ti/drv/sciclient/examples/common/sciclient_appCommon.h>
    
    /* ========================================================================== */
    /*                           Macros & Typedefs                                */
    /* ========================================================================== */
    
    /** \brief Aligned address at which the X509 header is placed. */
    #define SCISERVER_COMMON_X509_HEADER_ADDR (0x41cffb00)
    
    /* ========================================================================== */
    /*                         Structures and Enums                               */
    /* ========================================================================== */
    
    /* None */
    
    /* ========================================================================== */
    /*                 Internal Function Declarations                             */
    /* ========================================================================== */
    
    /* None */
    
    /* ========================================================================== */
    /*                            Global Variables                                */
    /* ========================================================================== */
    
    /* None */
    
    /* ========================================================================== */
    /*                          Function Definitions                              */
    /* ========================================================================== */
    
    #if defined(SOC_J7200)
    static void setMpuFrequency(void)
    {
        int32_t cslRet = CSL_EFAIL;
        int32_t tisci_dev_id = TISCI_DEV_A72SS0_CORE0_0;
        int32_t tisci_clk_id = TISCI_DEV_A72SS0_CORE0_0_ARM_CLK_CLK;
        int32_t slave_clk_freq_hz = 1200000000;
        uint64_t respFreq, currentFreq;
        uint32_t regRdVal;
    
        cslRet = Sciclient_pmQueryModuleClkFreq (tisci_dev_id,
                                                 tisci_clk_id,
                                                 slave_clk_freq_hz,
                                                 &respFreq,
                                                 SCICLIENT_SERVICE_WAIT_FOREVER);
        if (cslRet != CSL_PASS)
        {
            App_sciclientPrintf("Sciclient_pmQueryModuleClkFreq...FAILED \n");
        }
        else
        {
            App_sciclientPrintf("Sciclient_pmQueryModuleClkFreq, DevId 0x%x @ %dHz... \n", tisci_dev_id, respFreq);
        }
    
        /* PLL8_HSDIV0 output is selected and output to MAIN_PLL8_HSDIV0_CLKOUT */
        CSL_REG32_FINS(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_WAVE_SEL, 0x1);
        App_sciclientPrintf("PLL8_SS_CTRL Register Value = 0x%x \n", CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL));
    
    #if 0
        /* OBSCLK0_MUX1_CLKOUT = MAIN_PLL8_HSDIV0_CLKOUT / DIV8 */
        CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK1_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK1_CTRL_CLK_SEL, 0x1);
        App_sciclientPrintf("CTRLMMR_OBSCLK1_CTRL Register Value = 0x%x \n", CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK1_CTRL));
    
        /* OBSCLK0_MUX0_CLKOUT = OBSCLK0_MUX1_CLKOUT. The clock is divided and output to the OBSCLK[2:0] pins */
        CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_SEL, 0xD);
    
        /* OBSCLK0 output clock is divided by 2 (clkdiv = 1). The maximum supported frequency is 200 MHz */
        CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_DIV, 0x1);
    
        /* Load the new divider value */
        CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_DIV_LD, 0x0);
        CSL_REG32_FINS(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL, MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_CLK_DIV_LD, 0x1);
    
        App_sciclientPrintf("CTRLMMR_OBSCLK0_CTRL Register Value = 0x%x \n", CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL));
    #endif
    
        App_sciclientPrintf("Sciclient_pmSetModuleClkFreq, DevId 0x%x @ %dHz... \n", tisci_dev_id, slave_clk_freq_hz);
        cslRet = Sciclient_pmSetModuleClkFreq(tisci_dev_id,
                                              tisci_clk_id,
                                              slave_clk_freq_hz,
                                              TISCI_MSG_FLAG_AOP,
                                              SCICLIENT_SERVICE_WAIT_FOREVER);
        if (cslRet != CSL_PASS)
        {
            App_sciclientPrintf("Sciclient_pmSetModuleClkFreq...FAILED \n");
        }
    
        cslRet = Sciclient_pmGetModuleClkFreq(tisci_dev_id,
                                              tisci_clk_id,
                                              &currentFreq,
                                              SCICLIENT_SERVICE_WAIT_FOREVER);
        if (cslRet != CSL_PASS)
        {
            App_sciclientPrintf("Sciclient_pmGetModuleClkFreq...FAILED \n");
        }
        else
        {
            App_sciclientPrintf("Sciclient_pmGetModuleClkFreq, DevId 0x%x @ %dHz... \n", tisci_dev_id, currentFreq);
        }
    
        regRdVal = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL);
        App_sciclientPrintf("CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("BYPASS_SW_OVRD Field Value = 0x%x \n", CSL_FEXT(regRdVal, WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD));
        App_sciclientPrintf("BYP_WARM_RST Field Value = 0x%x \n", CSL_FEXT(regRdVal, WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_BYP_WARM_RST));
        App_sciclientPrintf("CLK_SEL Field Value = 0x%x \n", CSL_FEXT(regRdVal, WKUP_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_CLK_SEL));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL0);
        App_sciclientPrintf("PLL8_FREQ_CTRL0 Register Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("FB_DIV_INT Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL0_FB_DIV_INT));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL1);
        App_sciclientPrintf("PLL8_FREQ_CTRL1 Register Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("FB_DIV_FRAC Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL1_FB_DIV_FRAC));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL);
        App_sciclientPrintf("PLL8_DIV_CTRL Register Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("POST_DIV2 Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL_POST_DIV2));
        App_sciclientPrintf("POST_DIV1 Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL_POST_DIV1));
        App_sciclientPrintf("REF_DIV Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL_REF_DIV));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL);
        App_sciclientPrintf("PLL8_SS_CTRL Register Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("BYPASS_EN Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_BYPASS_EN));
        App_sciclientPrintf("WV_TBLE_MAXADDR Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_WV_TBLE_MAXADDR));
        App_sciclientPrintf("RESET Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_RESET));
        App_sciclientPrintf("DOWNSPREAD_EN Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_DOWNSPREAD_EN));
        App_sciclientPrintf("WAVE_SEL Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_CTRL_WAVE_SEL));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD);
        App_sciclientPrintf("PLL8_SS_SPREAD Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("MOD_DIV Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD_MOD_DIV));
        App_sciclientPrintf("SPREAD Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD_SPREAD));
    
        regRdVal = CSL_REG32_RD(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0);
        App_sciclientPrintf("PLL8_HSDIV_CTRL0 Register Value = 0x%x \n", regRdVal);
        App_sciclientPrintf("RESET Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_RESET));
        App_sciclientPrintf("CLKOUT_EN Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_CLKOUT_EN));
        App_sciclientPrintf("SYNC_DIS Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_SYNC_DIS));
        App_sciclientPrintf("HSDIV Field Value = 0x%x \n", CSL_FEXT(regRdVal, MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0_HSDIV));
    }
    #endif
    
    int main(void)
    {
        int32_t ret = CSL_PASS;
        Sciclient_ConfigPrms_t clientPrms;
        Sciserver_TirtosCfgPrms_t appPrms;
    
        /* Sciclient needs to be initialized before Sciserver. Sciserver depends on
         * Sciclient API to execute message forwarding */
        ret = Sciclient_configPrmsInit(&clientPrms);
    
        if (ret == CSL_PASS)
        {
            ret = Sciclient_boardCfgParseHeader(
                (uint8_t *) SCISERVER_COMMON_X509_HEADER_ADDR,
                &clientPrms.inPmPrms, &clientPrms.inRmPrms);
        }
        
        if (ret == CSL_PASS)
        {
            ret = Sciclient_init(&clientPrms);
        }
    
        if (ret == CSL_PASS)
        {
            ret = Sciserver_tirtosInitPrms_Init(&appPrms);
        }
    
        if (ret == CSL_PASS)
        {
            ret = Sciserver_tirtosInit(&appPrms);
        }
    
        /* Enable UART console print*/
        if (ret == CSL_PASS)
        {
            App_sciclientConsoleInit();
        }
    
    #if defined(SOC_J7200)
        setMpuFrequency();
    #endif
    
        App_sciclientPrintf("Sciserver Built On: %s %s\n", __DATE__, __TIME__);
        if (ret == CSL_PASS)
        {
            App_sciclientPrintf("Starting Sciserver..... PASSED\n");
    
            uint32_t freqHz;
            Sciclient_pmGetModuleClkFreq(TISCI_DEV_GTC0, TISCI_DEV_GTC0_GTC_CLK,
                (uint64_t *) &freqHz, SCICLIENT_SERVICE_WAIT_FOREVER);
            App_sciclientPrintf("GTC freq: %d\n", freqHz);
    
            BIOS_start();
        }
        else
        {
            App_sciclientPrintf("Starting Sciserver..... FAILED\n");
        }
        return ret;
    }
    
    /* ========================================================================== */
    /*                 Internal Function Definitions                              */
    /* ========================================================================== */
    
    /* None */
    
    

    The Sciserver test application was built with the following commands.

    cd ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/build
    make -s sciserver_testapp_clean BOARD=j7200_evm CORE=mcu1_0
    make -s sciserver_testapp BOARD=j7200_evm CORE=mcu1_0

    The following application image was used to run the Sciserver test application on MCU1_0.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/binary/sciserver_testapp/bin/j7200/sciserver_testapp_mcu1_0_release.rprc

    The multicore image was generated with the following command.

    ~/ti/ti-processor-sdk-rtos-j7200-evm-07_02_00_06/pdk_j7200_07_01_05_14/packages/ti/boot/sbl/tools/multicoreImageGen/bin/MulticoreImageGen LE 55 output.appimage 0 sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release.rprc 4 sciserver_testapp_mcu1_0_release.rprc

    Best regards,

    Daisuke