AFE7799: JESD Initialization

Hello John,

John Show said:

The JESD receiver should generate synchronization request by asserting SYNC~ signal.

Yes, this is correct. The JESD204 receiver on the AFE7799 TX DAC side will generate SYNC~ signal on dedicated LVDS SYNC or CMOS SYNC pins. You will have to look at the GPIO mapping on your configuration file to find out the pins assigned for the LVDS SYNCOUT or CMOS SYNCOUT pins.

John Show said:

In our RU system, we don't see the AFE7799 assert SYNC~ signal when initialization, and our FPGA asserts SYNC~ when initialization.

When you are completing the bring-up of the AFE7799 or perform ADC DAC SYNC, you should be able to see the SYNCOUT toggle from logic high to logic LOW. logic LOW is a sync request to request your FPGA to send out K28.5 handshaking characters. Once FPGA and AFE7799 TXDAC completes handshake over JESD204B, the SYNCOUT will become logic HI

John Show said:

1. Is the one way SYNC~ enough? It means FPGA for JESD Rx assert SYNC~ and AFE7799 for JESD Tx can cover synchronization of the reverse direction?

If you mean one way SYNC~ means FPGA send out SYNCOUT for the AFE7799 RX uplink (JESD204 TX for the AFE), then one way SYNC~ is not enough. You need two way SYNC 

See diagram below:

https://www.ti.com/lit/an/sbaa422/sbaa422.pdf

John Show said:

2. If not so, how to start the synchronization? i.e. how to make AFE7799 assert the SYNC~ signal

You can utilize C API adcDacSync(1)