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AWR1843: Timing Parameters of NERROR_OUT

Part Number: AWR1843

Team,
My customer who employs the AWR1843 for their solution has a question regarding the NERROR_OUT pin. Also learned the error condition causing NERROR_OUT to assert via useful thread.
Could you please let me confirm the following regarding the operation at the time of abnormality assertion (NERROR_OUT=Low).

1) Time from the occurrence of an error to the High to Low switchover
2) Minimum holding time of Low state
3) Does the AWR1843 stop in the Low state?
4) Condition for releasing Low state


Could I have your comment on these questions?

Thank you for your support.
Regards,
Nonaka

  • Team,
    Its been one week. Are there any update?
    Regards,
    Nonaka

  • Hi,

    Please find my comments below.

    1) Time from the occurrence of an error to the High to Low switchover

    Hardware error reporting is typically < 1us.

    2) Minimum holding time of Low state

    Minimum holding needs to be calculated as per TRM section 29.2.2.2. 

    It will be: 

    low time = T (VCLK) * (LTCP +1)

    T (VCLK) = time period of the peripheral clock

    LTCP = Low-Time Counter Preload register value as specified by the user

    3) Does the AWR1843 stop in the Low state?

    Once the Error pin is asserted, it is suggested to issue a reset to the device. Error pin is asserted only in case of CPU aborts or a severe failure. In Cpu abort condition reset is the only option and in severe failure condition the 1843 will is not considered safe for use and may enter an abort as well. So as per the safety guidelines it is suggested to issue reset to the device on error pin assertion.  

    4) Condition for releasing Low state

    Once the ERROR pin outputs low (error detected condition), a power on reset or a write of 0x5 to ESMEKR is required to release the ESM error pin back to normal state.

    Thanks,

    Pradipta.