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Original question:

TMUX7462F: Supplying the VFP pin with a series diode

TMUX7462F: Supplying the VFN with 0.5V ?

İbrahim Mete
Prodigy 50 points
Part Number: TMUX7462F
Other Parts Discussed in Thread: TMUX741-746EVM

Hi,

About the "Supplying the VFP pin with a series diode" topic,  the answer includes "VFN at 0.5V then the clamping voltage should be around -0.2V".

I have just noticed the VFN recommended range specified Vss to 0V and the absolute MAX is 0.3V in the datasheet.

And this mean if Vss and GND connected together then it looks like VFN also must be connected to the GND/VSS, and then the negative protection will be GND-0.7V.

I want to protect 5V level signals in the GND-0.3V and VDD+0.3V range. But how should I design "GND-0.3V" ?

Can I connect 0.4V to VFN pin? Or Do I have to shift the chip GND and VSS levels below 0V to provide -0.3V protection?

What solution would you recommend for this?

It would be better if the VFN/VFP is not restricted by 0.7V in the chip design or at least if it is 0.3V instead of 0.7V I think.

Regards,

Mete

  • 0
    TI__Mastermind 28978 points

    Hey Mete, 

    Are the over/undervoltage events you're concerned about DC shorts? 

    Good catch on that. Yes, it looks like if you maintain the GND at 0V and VSS up to 0.5V you would be violating the abs max here. This would probably cause some internal leakage or damage so we'll want to avoid that. I would recommend shifting the GND and VSS levels up here. 

    İbrahim Mete said:
    Or Do I have to shift the chip GND and VSS levels below 0V to provide -0.3V protection?

    I believe you'd want to shift these Above, not below the 0V. If you want 0.3V protection, you'd want 0.4V with the 0.7V drop.

    It gets a little more confusing here on the ground shifting when you look at the VFP but if you shift up the ground to 0.4V, then your device would see 0.4V less on the positive supply and to accommodate for the 0.7V drop you would want a 3.9V signal on the VFP (relative to ground) for the device to trigger a fault at 5V.   

    I would still recommend testing this on an EVM board as well though to insure that it behaves as intended, especially depending on the precision of the cutoff you're looking for and some tricky math on the ground shifting front. The TMUX741-746EVM can support this.

    Thanks,
    Rami

  • 0 in reply to Rami Mooti1
    Prodigy 50 points

    Hi Rami,

    Thanks for the reply. Yes, it is DC shorts, and the shift level should above instead of below. 

    Could you review the schematic in the picture is OK? 

    All the written voltages referenced to the system ground. VFN node is the shifted chip ground and no connected to anywhere outside the picture.

    VFN node can be in 0.4 to 0.7V range. As far as I understand, total chip supply current 0.3mA to 0.5mA range(please confirm this). 1N4448X (datasheet) forward voltage drop is look like 0.4V to 0.7V in the 0.1mA to 10mA range. So the pins can be negative protected -0.3V to GND according to diode voltage drop.

    I think the VFP supplied by 4.6V to protect the pins up to 5.3V like in the previous thread.

    I want to ask;

    1) Is this design OK? 

    2) Are the capacitors enough? Lower component count preferred.

    3) Any capacitor needed between the VFN node and the system GND (parallel to the diode)?

    4) For the VSS pin, is this design OK? or would it be better if connecting the VSS pin to the system Ground and adding a capacitor between VSS and GND pin (parallel to the diode)?

    Regards,

    Mete

  • +1 in reply to İbrahim Mete
    TI__Mastermind 28978 points

    Hey Mete,

    I reviewed the schematic and have the following notes based on your questions :
     

    1) Is this design OK? 

    Design for the most part looks good with some points on #3 and #4

    2) Are the capacitors enough? Lower component count preferred.

    The capacitors that are on the current schematic are fine but I would add one more (covered in #3 and #4)

    3) Any capacitor needed between the VFN node and the system GND (parallel to the diode)?

    A capacitor would be recommended. This can be used to hold local charge in case of any in rush current, so I would add this here.

    4) For the VSS pin, is this design OK? or would it be better if connecting the VSS pin to the system Ground and adding a capacitor between VSS and GND pin (parallel to the diode)?

    VSS pin in design is okay and will function fine but I think it would be a better idea to tie VSS to system GND. Running at the rails may give higher leakage so if we give a wider range of operation we can try and avoid this. A cap wouldn't be necessary here though since VSS and GND are tied together already. 

    So just to reiterate, adding a cap to VFN node to system ground and tying VSS to GND is recommended. Aside from that, the schematic looks good.


    Another thing I want to note here is the VFP level at 4.6V is correct and my math was incorrect from the previous post. Just wanted to confirm that we're on the same page on that as well. 
    Additionally, it's important to know that there may be some device process variations so how tight the threshold is can't be guaranteed.  

    Thanks,
    Rami

  • 0 in reply to Rami Mooti1
    Prodigy 50 points

    Hi Rami,

    Thanks for your recommendations. 

    Regards,

    Mete