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TAS5631 never ready

sst
Prodigy 50 points
Other Parts Discussed in Thread: TAS5631

Hi, 

 

I have a circuit based on TI reference design for this ic, everythings seems OK, but the READY pin remains low.

=> Reset si pulled high 1s after power up

=> OTW, SD, and CLIP are all high

what are the conditions under which ready is down and otw, sd, and clip high ?

 

I'm a little bit lost, as I've doule checked eveyrhting, and even change the 2 processor (tas5631 and driver uc)

 

Stephane

  • 0
    TI__Guru**** 189401 points

    Hi, Stephane,

    What about /RESET? It needs an external pull-up or be driven high by logic.

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 50 points

    Hi, 

     

    Reset is driven by the main uc (a pic).

    The uc pull it high (checked on the proto board) as soon as it is ready (~0.5s after power up).

     

    Other ideas ?

     

    Stephane

  • 0 in reply to sst
    Prodigy 50 points

    Other info : 

    - on the Osc_adj pin (1) I have 1.09V

    - on RESET, I have the 3.18V signal from the uc

    - on c_startup, I have 0v (?)

    - on the A,B,C,D inputs, I have no signal (the uc waits for the ready pin). I I send a signal even if ready is down, nothing happens

    - on VI_CM, I have 0v

    - on Vreg, I have 3.18V

    - on OTW1,OTW2, SD,CLIP, I have 3.12V

    - on READY, I have 0v

    - on M1,M3, I have 0v, on m2, I h&ve 3.18V 

    - VDD and GVDDs (via 3.3R) are 12.6V

    - PVDD is 12.6V (could that be the problem as it is in the absolute rating range, but outside recommended range ???)

    - PSU_REF is 500mV

     

     

     

  • 0 in reply to sst
    TI__Mastermind 18510 points

    Stephane, TAS5631 will not operate at PVDD = 12.6V.  Below 25V its undervoltage protection shuts it down.  Try PVDD = 25 to 52.5 Vdc as shown in the data sheet.  (In general, Recommended Operating Conditions in our data sheet must be met for a device to operate properly and reliably.

    (In operation we expect V.C_STARTUP = Vreg.  With PVDD 50V we expect VI_CM and PSU_REF ~= 1.9V, and with PVDD 25V we expect half of that.)

    Maybe there is a short on C_STARTUP or VI_CM, but this seems unlikely.  I expect correct PVDD will solve the problem.

    Best regards,

    Steve.

  • 0 in reply to SteveCrump
    Intellectual 450 points

    BTW the TAS5631 needs a correct PWM signal to be present to singnal "ready" in the first place. For a Mute PWM singal this means 50% modulation all the time.

  • 0 in reply to Christopher K.
    Prodigy 60 points

    Hello,

    does it also needs a valid signal to make the /SD pin high??

    My /SD pin is always low.

    regards,

    sebastian

  • 0 in reply to Sebastian Uchman
    Prodigy 60 points

     Hi, 

    I noticed that even if I pull the /RESET low, /SD stays low.

    I read in datasheet on page 23:

    "Asserting the reset input low removes any fault information to be signaled on the
    SD output, i.e., SD is forced high."

    Does it mean, there is something wrong with the TAS5631 and I should replace it?

    Regards, 

    Sebastian