TAS5630 abnormal failure

Thanks Don / Steve,

My application is a power amplifier with RCA input, in this preamplifier where I have one gain control more two analog 12dB/8ª  filter. But the end user sure will connect/disconnect the cable without power-off the amp, also damaging the device.
But i will test the input stage as TAS5630 EVM, supplied by +12V. 

If i use an zener diode (as clamp...) to protect input against this large transient?

Best Regards,

Paulo

Hi Steve,

Thank you for your fast reply.

I will test the 4.7V zener into all inputs.

Yes, I think this can protect the TAS against large transientes on plug/unplug audio cable. But before this I also will change the preamp supply from +/-15V to +12V.

I will keep you informed about the test results.

Regards,

Paulo

Paulo, did these changes help with reliability?

I tried the 4.7V Zener trick and found that it increased the DC output voltages. I don't have the measurements now, but nominal calculations show that each output should have about 0.5 Vdc shift for each uA of leakage at its respective input (33 kohm input resistance times voltage gain of 15). Leakage of the 1N5230B Zener diodes I was using was about 1.3 uA when biased to about the same DC voltage as the AC-coupled inputs of a TAS5630 with no input signal. It affects the maximum undistorted output power of the TAS5630.

Russ

Dear Russel,

I fixed this bug using single-supply (+12V) on the analog front end, as recommended by Texas. Yes, I tried to use zeners (4.7V) to clamp, but using the symmetrical supply for analog front end (+15V / -15V) I still have negative spikes (the TAS is tolerant to only -0.3V negative spikes) that can damage the device.

Using single-supply analog for op-amps (pre-amplifiers), the circuit works fine, without problem, high reliability (I don´t burn more devices!)

Regards,

Paulo

Hi steve.

I have a question.

So when I add zener diode to each TAS5630, Can I add zener diode to each C58,C59 paralley?

I am using PBTL type now.

What if I use zener diode 5.1V insteaded of 4.7V?

Please ....

Regards.,

junho

Dear eveyone.....

One more thing.....

I often get spark and burn on I.c pin 42,43 connecting to PVDD

after this happened I could find  C 30 connected to I.C pin 39,38 and ground got crack at the soldering

What happens? and what is the best solution that I can get for this problem?

Please let me Know.....

Best regards.....

Junho

Dear Junho,

This happens also here with my boards - some boards I had the IC burning and sparks between PVDD and OUTPUT pins, as you can see into images bellow. In the most cases, the problem happened when the PCB is powered the 1st time (with load connected)

But in all cases the decoupling caps (2,2uF 100V X7R) was Ok. And the startup sequence is following the recomended. This is a misterious problem, I am working to solve this.

Best regards

Hi Paulo

I am using TAS 5630 PHD now.

How often do you get this type of problem?

(Like one out of 100 or.....)

Best regards,

Junho

Junho, I believe you are using a TAS5630PHD2EVM for all your work.  Is that correct, or are you using your own PCB layout and your own circuit?

Are you having difficulty with input plug/unplug as Paulo did?  If you are, maybe the correct power supply for the preamp can solve it.  Paulo has shown that zeners are not necessary when the preamp power supply is +12V single ended and the startup sequence is correct.  Still, you are right that the zeners would be added in parallel with C58 and C59 in the TI EVM (and C60 and C72 for BTL operation).  And I think 5.1V may be OK, but 4.3V would be better.  But please note Russell May's comment about leakage in zeners that can upset DC bias at the amplifier output.  It would be necessary with any zener to make sure its leakage was far less than 1uA when its voltage was 2V, the bias voltage for TAS5630 with PVDD 50V.

Junho and Paulo, I will try to comment on sparks at PVDDx and OUTx.  As Paulo says, they are mysterious.  I do not know a cause for this immediately, unless there is some power supply overvoltage during turn-on.  Is that possible?  Can each of you check that and let me know?  (I ask this because we have seen cases with spikes on power supply output as high as 80V.  Maybe these last only 10 or 20 uS, but that is long enough to damage an IC.)

Junho, I think the crack in C30 must be mechanical.  Maybe the PCB was flexed hard?  I do not know of an electrical event that can cause such a crack.

Best regards,

Steve.

Dear Junho;

The average of burned TAS with this problem is about 2~3 percent, which I consider a high incidence...
The best layout is the same as EVM, including positioning of parts and parts specifications. These 2,2uF X7R capacitors need to be high-quality.


Dear Steve, as I have tested the best way is the use of single supply, up to +12V biased with 1/2vcc. Since of zener's leakage can increase the DC 

offset at output of amplifier, also all zener are heat sensitive, so this zener's leakage can change with temperature change.

Regarding the TAS damage (burning) , the replacing of burned part solve the problem. Misterious, very misterious...

Best regards



Paulo

Dear Steve....

Thanks for soonest answer!

Yes I use my own PCB layout & circuit but there are almost the same as TAS5630PHD2EVM.

I have been following Paulo's method.

Since, you told me what to do (checking overvoltage)

Yes, I fully agree on what you're suggesting now.

First of all. Let me get some more experiments on this project and I will let you know later.

Let me ask you one more time about C30.

If I have C30 without soldering or with cracks on it does IC get sparks? (Burn out ?)

Additional....

To solve the problem on TAS5630 Hi input level.

Can I reduce supply voltage of OPA1632 U15 (12V) to 4V?

Thanks for all the trouble you have been talking for me.

Sincerly...

junho KIM

Paulo, I reviewed the photo of your PCB that you included in your last post, and I think there is much higher inductance in the connections between the decoupling caps and the IC than there is in the EVM.  I have attached a report showing the differences.  I have seen similar problems in PCB layouts, and in some cases these can make switching spikes on outputs and PVDD connections 3 times as high as they are in the EVM.  I do not know if this is true in your layout, but this can be destructive to the IC.

However, before we conclude that a PCB change is needed, I also noticed no evidence of thermal grease / compound on the top of the burned IC.  Maybe you are using thermal compound and removed it before taking the photo.  (We recommend a thin layer of a high performance thermal compound, as noted in Note 2 of the section PACKAGE HEAT DISSIPATION RATINGS on page 3 of data sheet SLES220B for TAS5630.)

However, some customers test without a heatsink in place, and others use thermal pads instead of themal compound.  Thermal pads isolate the IC heat slug from the heatsink, and they do not seem to have the thermal conductivity of a good thermal compound.  The problem with either testing without the heatsink or using a thermal pad is that the heat slug does not have a good path to ground.  The IC depends on a good path from the heat slug to ground to shunt currents that may be driven into the substrate during switching transitions.  Without a ground path those currents can flow anywhere through the substrate, and they can disrupt operation of the IC.

My question to Junho and Paulo then is, do you test without the heatsink in place? or are you using a thermal pad instead of thermal compound?  If the answer is yes, this can cause the problems you have been seeing.

Please let me know about this.

Best regards,

Steve.

Dear Steve,

Thank you for fast reply.

Due to layout limitation, the decoupling 2,2uF caps was placed about 5mm far from the IC. But I think so improve the layout when as possible - but not close as the EVM because some layout mechanical issues (in my project I cannot use double-sided component placing because the PCB is double-sided but components are assembled only in TOP layer, different of Texas EVM wich have components assembled in both sides).

You can't see the thermal grease because the IC was carefully cleaned before I taking the picture. And the IC have a direct contact with aluminum heatsink, without thermal pads, only a thin layer of thermal grease is applied. When this failure occurred, the IC had heatsink attached.

I remember which only the first procedure of board testing is made without heatsink - At this step, we check only the input / output signals without load into output. If pass, the heatsink is attached and the board is tested again, with load and at rated power.

Can the first test procedure damage the device?

Best regards

Paulo

Paulo, I will recommend copying the EVM as completely as possible when you improve the layout.  You can bring the BST caps to the top layer, but please push the close decoupling caps as close to the IC as possible, and please follow the routing of outputs, PVDD and PGND in the EVM to produce the lowest inductance connections.

Connections to the BST caps are not so critical, because they do not carry the heavy currents that the output and power traces carry.  Of course, keep BST traces as short as possible, but it is OK to use a short trace on bottom layer with a via at each end for BST caps A and D.

I think it may be possible to damage an IC in the test condition you described above, so that it fails later.  We don't know this for certain, though.  An open load condition is not benign - there is an impedance notch at the resonant frequency of the filter, and this can generate very high currents if the output signal contains any harmonic at the resonant frequency.  This can happen with outputs in clipping, because those signals include a very strong harmonic series.

We can't be sure if this test condition could damage ICs, but it is not a good condition.  Maybe the heatsink can be grounded temporarily somehow during the test?

Best regards,

Steve.

How are you...

It's me again.

1) Tahnk you for your assist. but I still want to know about "SD LED's  turning itself ON.

What, if there is any, causes the damage on pin55?

2) About C25, thank you so much.

3) About the power supply voltage. Thank you very much.  5 or 6Volt was ok.

 when I use supply voltage 5volt,should I need to change each polarity of C14,C15?

Best Regards

Junho.

Junho, I recall that you said this in another post:  --- After 4 hours of general operation "SD" LED turn on itself.  I found that R29 (3.3ohms) connecting to GVDD_A (pin 55 of TAS 5630 PHD) changed its color black as if it got burnt out.  The voltage of the pin 55 was 6 volt (12V is a normal voltage). ---

There is certainly damage to the IC if GVDD_A is stuck at 6Vdc.  That will drive /SD low, and that will turn on the SD LED.  But I think the damage starts with some overvoltage or other problem.  I think it does not start at GVDD_A.

I have not seen what voltage you are using for PVDD, but if it is 40 or 50 V I think maybe a 5V power supply to OPA1632 is a little low.  OPA1632 saturation drops are typically about 2V total with the TAS5630 as load, but they may somewhat higher.  But with a 5V power supply even 2V saturation loss leaves only 3V differential output.  TAS5630 minimum gain is around 23dB, ~x14.  With that gain, when OPA1632 clips TAS5630 will output only ~42V peak, so it may not reach full output in clipping.  So I will recommend 6Vdc power supply to OPA1632, unless you are using less than 40V for TAS5630 PVDD.

With 5 or 6 Vdc power supply to OPA1632, its DC bias point will be 2.5 or 3 Vdc, and this is still higher than DC bias at input of TAS5630, even with PVDD ~50V (there, input bias is near 2Vdc).  So the polarity of the input caps does not change.

Best regards,

Steve.

Steve, is there any reason not to design for X7R surface-mount ceramic (non-polar) input capacitors? They are available in 1206 and 1210 sizes and seem reasonably priced.

Russ

Russell,

X7R caps contribute to THD at low frequencies. the TAS5630 is high performing enough that you see a difference between ceramic and electrolytic. So, we use electrolytic on the EVM. if you're not as concerned with THD, then ceramics are fine.

-d2

Thanks for reminding me of the distortion differences. Can you reference any objective distortion comparisons between 10uF X7R caps and tantalum caps at low frequency? The only similar comparison I have seen is at http://industrial.panasonic.com/ww/i_e/21088/smd-film-capacitor_e/smd-film-capacitor_e/data/02.html. It shows that 1uF X7R caps have less distortion than 1uF tantalum caps at about 400Hz or less. Above 400Hz, the tantalum caps are better. 50 to 400Hz is the frequency range that I am interested in, but I don't know how different the results would be for 10uF caps and TAS5630 input loads in PBTL mode.

Another thing I wonder about is leakage. I am pretty much stuck with using 16V 1206-size caps for now. Tantalum leakage rating (for Kemet T491A106K016AT) is equivalent to about 8Megohms at 20 degrees C. 10uF X7R leakage rating can be much better (100Megohms for AVX, 50Megohms for Kemet, but only 5Megohms for Murata, for examples). With about 4VDC of bias, the AVX X7R caps could be expected to have up to about 0.50-0.04=0.46uA less leakage than these tantalum caps. That could lower the TAS5630 output voltages by about 0.23VDC at room temperature. DC output voltages of all of the several EVM's I have, are a little less than half of their 48VDC supply. Lower input capacitor leakage should raise their DC outputs closer to half of the power supply voltage, which might allow slightly higher symmetrical output voltage swings.

Russ