DRV8842 Operation

Chihiro,

I assume you have a pull-up resistor on nFAULT, correct?  When this condition happens, what is the voltage measured on V3P3OUT?

Also, I don't see any bulk decoupling on the VM supply.  Really don't think it affects what you are seeing, but it would be good practice to add a 100uF electrolytic to stiffen the supply up under heavy load conditions.

I will investigate this internally and post again once I determine other things to check or an explanation.

Hi Ryan,

Yes, the nFAULT pin has a pull-up resistor (here is a more detailed view of the schematic.  The U5, U3, and U4 components are all optoisolators to separate the 12 V plane from the rest of the board, which is 3.3 V). 

When the 3.3 V power supply is cut off, and at the same time the nFAULT goes low, the V3P3OUT also goes low.  After the 3.3 V supply is turned on again, the V3P3OUT remains at 0 V and the nFault goes up to around 600 mV, which isn't enough for the board to activate again. 

Thank you, and I really appreciate your help.

Hi Chihiro,

When you see this event, are you trying to run the motor? If so, can you disconnect the motor and see if nFault rises when 3.3V supply is turned on?

Can you also capture and send scope shots of the signals nSLEEP, nRESET, V3P3OUT, and nFAULT when powering up?

By the way, is C4 and C5 polarized? If so, please use non-polarized capacitors.

Thanks.

Hello Rick,

When I see this event, I am not trying to run the motor.  Right now, there is no load (except for the wire) that is connected to the OUT1 and OUT2 outputs from the DRV8842 H-bridge motor driver.  The nFAULT signal rises to around 900 mV when the 3.3 V supply is turned on, but not enough for proper function of the H-bridge.  When the 3.3 V is applied first and then the 12 V is reset, the nFAULT signal rises to its proper value (around 3.5 V).

This is a scope capture of the signals nSLEEP, nRESET, V3P3OUT, and nFAULT, as well as the 3.3 V input.  Since nSLEEP and nRESET lines are connected, they are shown as one capture line.

C4 and C5 are non-polarized capacitors.  I use Multilayer Ceramic Capacitors (parts C1608X7R1E104K and C1608X7R1E103J), which are not polarized.  

Thank you.

Hi Chihiro,

Thanks for the scope capture. I have a few additonal requests to help debug, if you don't mind.  I would like to see what happens when nFault cannot interfere with the control signals. The schematic shows that if nFault goes low, it can pull nSLEEP, nRESET, and I4 to another voltage. By providing a separate 10k pullup to 3.3V on nFault, it should be possible to determine if the problem is the control signals or interference from nFault.

1) Can you get a scope capture of VCP when turning on the 3.3V supply and the 8842 is already powered up?

2) Can you drive 3.3V directly to pin 1 of  R6 in your schematic? I suggest that you place a 1k resistor in series with the 3.3V (or limit the current ) when you do this. I would like to see a scope capture then. 

3) If the problem goes away, please zoom in to the nSLEEP, nRESET, and I4 pins looking for voltages above the maximum allowable voltage of 7V.

4) If the problem is still there, please remove resistor R7 and try step 2 again.

5) If the problem goes away in step 4, please tie a 10k resistor from 3.3V to nFAULT and capture nFAULT when the device is coming out of sleep. You should be able to tie R7 pin 2 to V3P3OUT assuming that 330uA is enough current for the optoisolator.

Thanks.

Hello Rick,

The scope capture of VCP when turning on the 3.3 V supply after the 8842 has been turned up can be seen here.

I tried your step 2 suggestion, and in this configuration the problem goes away.  The scope capture when 3.3 V is tied to a 1k resistor, which is tied directly to pin 1 of R6, can be found here. Line 1 (the yellow line in the capture) is the node which is connected to nSLEEP, nRESET, and I4.  The problem seems to go away in this configuration, with VCP and nFAULT going high when 3.3 V is turned on after 8842 has been on (maintaining the same voltage as when 12 V is turned on after 3.3 V has been on). 

I looked for voltages above the maximum 7 V for nSLEEP, nRESET, and I4, but the maximum voltage from this line was 3.272 V.  This leads me to believe that my U5 optoisolator could be the possible culprit?

Hello Rick,

From trying out step 2, I thought that the problem was possibly in the optoisolator, so I isolated the optoisolator and debugged without the DRV8842. I started a new board and put in R4, R5, and R6 as well as the U5 optoisolator, and it displayed normal behavior, where order of switching the 12 V or 3.3 V power supplies do not matter.  I then put in a new optoisolator on my current board with the DRV8842 on it, and it displayed the problems again.  Thus, it seems that the problem is somewhere in the interaction between the configuration of the optoisolator and the DRV8842. 

I tried your suggestion for step 4, removing the resistor R7 and measuring VCP and nSLEEP/nRESET/I4 nodes, but it displays the same problem behavior as before, where order of apply 3.3 V power and 12 V power supplies do matter. 

Thank you.