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DRV8302 Fault

Other Parts Discussed in Thread: DRV8302, TMS320F28035

Dear Friends,

I have used DRV8302, as an MOSFET Driver, in my design for BLDC Motor Control Board. 

We are generating 6 PWM signal from MCU (TMS320F28035), but we can't get output PWM pulses from DRV8302, due to FAULT pin = 0V, as it's active low. 

Also in my circuit, the voltage level at pin GVDD (internal gate driver regulator) is around 0.7V instead of around 10V. 

I have done following things:

  1. toggle En_Gate pin (which is pull down with 1K resistor),
  2. tied GVDD pin with OC_ADJ pin to disable Over Current Trip via 100K resistor. 
I think, if I get proper voltage level at pin GVDD, then FAULT will be removed. Because, as I make En_Gate pin = 1, from watch window, immediately FAULT pin = 1, but as I apply En_gate = 0, Fault will be = 0.7V approx.  
  • Hi Chinmay,

    Can you clarify your statement 2? Do you tie GVDD or DVDD to disable overcurrent? You should use DVDD. Using GVDD will violate the absolute maximum voltage on  the OC_ADJ pin.

    For reference, please refer to the hardware files of the DRV830x-HC-KIT. The link is http://www.ti.com/litv/zip/sloc292

    If you get the proper voltage at GVDD, FAULT will be removed if it is the only fault detected. Please examine pages 14 and 15 of the datasheet for a description of faults.

    If you are still having problems, any additional information provided (schematics, layouts, scope captures, and exact sequences) will help us debug.

  • Thanks Rick.

    Yes you address my fault perfectly. I've tied OC-ADJ pin to GVDD instead of DVDD.

    Now, I've correct it, but still voltage at GVDD is around 0.7V, and FAULT pin is at 0V (active low). 

    Yes, I've look into the page number 3060.schematic pdf.pdf14-15 of datasheet to investigate the causes of FAULT. 

    Here I share my schematic &  the Layout in other reply as I can insert only single file so? 

    The sequence of program loading is, I'll load the code of HVPM Sen2100.schematic pdf.pdfsored from control suit in level 2, and from watch window, I'll first make EnableFlag variable from 0 to 1, then make En_Gate pin from 0 to 1. 

    As En_Gate becomes 1, the voltages at pin DVDD & AVDD will be 6.6 & 3.3, respectively, but voltages at pin GVDD becomes 0.7 instead of 10V approx. 

  • Dear Ricks,

    Here I can't inserted a layout design of my project as it has size of 40MB. 

    Can I send it to your Email ID? Please give me ur ID. 

  • Hi Chinmay,

    Is it possible that the device was damaged due to violating the absolute maximum of OC_ADJ?

    Please check for proper operation of the charge pump when EN_GATE is 1. The CP1/CP2 pins should be toggling to pump GVDD to approximately 11V. If CP1/CP2 are not toggling, the device may have been damage, or something is prevent charge pump from working properly.

    If you do not see any reason for GVDD being .7V, I suggest you replace the device.

    I reviewed the schematic and noticed that the AGND of the DRV8302 is not directly connected to GND and PGND of the device. It is recommended that these pins are directly connected.

     

  • Dear Rick,

    Thanks for the suggestion. 

    I've connected 1uH inductor @ L2 in my schematic to short Virtual Ground. in this sense, L2 will short AGND & GND. 

    Now I got my FAULT, I've applied a compound tube between board & DRV8302 so compound layer prevent to connect GND to POWER_GND (pin # 57 of DRV8302). 

    Probably, I'll get result very soon. 

    Thanks for everything. 

    I'll accept your feedback for my schematic & layout design.