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Configure PCM1864 EVM for 16bits 16kHz 4 ch TDM with on board crystal

M Ho
Prodigy 230 points
Other Parts Discussed in Thread: PCM1864

Hi,

     I'm trying to configure my PCM1864 EVM to do 4 channel TDM recording. The codec is using on board crystal ( disconnect J8, J10, J11) as master clock. Whenever I configure the register for my target sample rate, the board stops working. (register 0x72 change to 0x1, which is wait clock stable). I have tried CLKDET_EN and manually set registers. I'm not sure what I missed. Can any one help me to review my settings?

Here is the manually setup of page 0 ( assume PLL is 98.304MHz, crystal is 24.576MHz)

0 1 2 3 4 5 6 7 8 9 a b c d e f
00: 00 08 08 00 00 86 41 41 42 42 00 df 01 00 00 08
10: 01 20 00 00 00 00 08 00 00 00 00 00 00 00 00 00
20: 3e 00 00 01 50 07 17 ff 01 01 00 08 00 00 00 00
30: 00 00 00 01 00 00 01 00 00 00 00 00 00 00 00 00
40: 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80
50: 7f 00 80 7f 00 80 7f 00 00 00 00 00 00 00 00 00
60: 01 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 70 10 01 01 47 45 11 44 07 00 00 00 00 00 00 00


Here is the auto setup of page 0

0 1 2 3 4 5 6 7 8 9 a b c d e f
00: 00 00 00 00 00 86 41 41 42 42 00 df 01 00 00 00
10: 01 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 11 00 00 01 50 07 05 ff 00 00 01 10 00 00 00 00
30: 00 00 00 01 00 00 01 00 00 00 00 00 00 00 00 00
40: 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80
50: 7f 00 80 7f 00 80 7f 00 00 00 00 00 00 00 00 00
60: 01 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 70 10 01 02 47 45 11 44 07 00 00 00 00 00 00 00

Thank you,

M Ho

  • 0
    Prodigy 230 points
    Hi,
    I have reviewed the TRM several times. On "table 10: PCM1864 Clock Divider and Source Control with External SCK", the highest SCK frequency of 16kHz is 12.288MHz. Does this mean the maximum frequency of XTAL for 16kHz is 12.288MHz? If I have a 24.576MHz crystal, it will not work in this frame rate?

    M Ho
  • 0 in reply to M Ho
    TI__Guru* 84915 points
    Hi, M Ho,

    We recommend to configure the external SCK as mentioned in Table 10 and Table 7 (External Master Clock versus Sampling Frequency). This will ensure that all the timing conditions will be respected.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 230 points

    Hi Luis,

         Can you please help me to understand how I can make it right? Table 7 is for 1860. I think this does not apply. From table 10, it states external SCK. I'm using the crystal connected to XI/XO. I have no SCK connected. Do you mean we must use SCK? If the crystal should work, how I can configure correctly? 

    Thank you,

    M Ho

  • 0 in reply to M Ho
    TI__Mastermind 27990 points

    Hi M,

    Please use the following script to enable 16 kHz 16 bit 4 channel TDM, with the PCM1864 running off the 24.576 MHz crystal. You need to enable manual PLL configuration and set the dividers accordingly, and choose the PLL as the clock source. You can copy and paste this script in the GUI and hit execute to use with the EVM.

    Fullscreen Master_16kHz_16bit_crystal_TDM.txt Download 
    #PCM1864 Master TDM 16 kHz from crystal
w 94 0B 4F
w 94 0C 01
w 94 20 B0
w 94 21 01
w 94 22 01
w 94 23 03
w 94 25 07
w 94 26 02
w 94 27 FF
w 94 28 01
w 94 29 01
w 94 2A 00
w 94 2B 08

    Justin