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TLV320AIC3204: I2S samples rate at 96khz/192Khz will cause the low frequency response output below -0.5dB

Arthur Huang
Expert 6065 points
Part Number: TLV320AIC3204

Hi team,

customer feedback that when they test the AIC3204 at 96Khz or 192Khz sample rate, they found the frequency response output in low frequency range is under -0.5dB, however the 48Khz will no have this problem.

Attached is their test report and test environment setup, please help to review it and advise if anything need to be considering. Thanks.

Regards,

Arthur


 


 

Audio 96k 192k fail.pdf

  • 0
    TI__Guru* 84915 points
    Hi, Arthur,

    Do you have the register configuration for 96K and 192K? These frequencies require of a different processing block and other conditions to work properly.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Expert 6065 points

    AIC3204_cfg.txt 
    ###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################


###############################################
# Clock Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.288 (48k) ~ 49.152 (192k) MHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NDAC = 1, MDAC = 2
w 30 0b 81 82
#
###############################################


###############################################
# Program the OSR of DAC to 128
###############################################
#
#
w 30 0d 00
w 30 0e 80
#
###############################################

###############################################
# Set the word length of Audio Interface to 
# 32bits PTM_P4
###############################################
#
#
w 30 1b 30
#
###############################################

###############################################
# Set the DAC Mode to PRB_P18 (filter type-C)
# (up to 192khz)
###############################################
#
#
w 30 3c 12
#
###############################################


###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# I2S to analog Setup
###############################################
# De-pop
w 30 14 25
#
# Set the Input Common Mode to 0.9V and Output 
# Common Mode for Headphone to Input Common Mode
w 30 0a 00
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Route LDAC/RDAC to LOL/LOR
w 30 0e 08 08
#
# Set the DAC PTM mode to PTM_P3/4
w 30 03 00 00
#
# Set the HPL/HPR gain to 0dB
w 30 10 00 00
#
# Set the LOL/LOR gain to 0dB
w 30 12 00 00
#
# Power up HPL/HPR and LOL/LOR drivers
w 30 09 3C
#
# Select Page 0
w 30 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
# power up DAC
w 30 3f d6
#
###############################################
    Hi Luis,

    Attached is the customer configuration register setting, please help to check if any mistake or concerns. Thanks.

    Regards,

    Arthur

  • 0 in reply to Arthur Huang
    TI__Guru* 84915 points
    Hi, Arthur,

    Thank you for the registers configuration.

    It seems that the OSR value is configured at 128. It is strongly recommended to use an OSR value at 32 when the filter C is used. This will allow to have good results with high sampling rates.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Expert 6065 points

    Hi Luis,

    attached is customer revised register setting, after customer revised the register 0x0E from 0x80 to 0x20, the test result is shown as below plot.

    it looked the low frequency is not improved, but the high frequency is got worse.

    Please help to have your comments if any. Thanks.

    Regards,

    Arthur

    8105.AIC3204_cfg.txt 
    ###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################


###############################################
# Clock Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.288 (48k) ~ 49.152 (192k) MHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NDAC = 1, MDAC = 2
w 30 0b 81 82
#
###############################################


###############################################
# Program the OSR of DAC to 128
###############################################
#
#
w 30 0d 00
w 30 0e 80
#
###############################################

###############################################
# Set the word length of Audio Interface to 
# 32bits PTM_P4
###############################################
#
#
w 30 1b 30
#
###############################################

###############################################
# Set the DAC Mode to PRB_P18 (filter type-C)
# (up to 192khz)
###############################################
#
#
w 30 3c 12
#
###############################################


###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# I2S to analog Setup
###############################################
# De-pop
w 30 14 25
#
# Set the Input Common Mode to 0.9V and Output 
# Common Mode for Headphone to Input Common Mode
w 30 0a 00
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Route LDAC/RDAC to LOL/LOR
w 30 0e 08 08
#
# Set the DAC PTM mode to PTM_P3/4
w 30 03 00 00
#
# Set the HPL/HPR gain to 0dB
w 30 10 00 00
#
# Set the LOL/LOR gain to 0dB
w 30 12 00 00
#
# Power up HPL/HPR and LOL/LOR drivers
w 30 09 3C
#
# Select Page 0
w 30 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
# power up DAC
w 30 3f d6
#
###############################################

  • 0 in reply to Arthur Huang
    TI__Guru* 84915 points

    Hi, Arthur,

    Did customer also modified the NDAC and MDAC values? If the OSR is modified, the N/MDAC dividers must be modified in order to get the correct sampling rate. Additionally, I also recommend to add a low-pass filter at the analog outputs. We recommend to add a 1kohm and 4.7nF low-pass filter in order to eliminate noise for measurement purposes.

    Finally, does customer have different results with a different processing block?

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 20 points

    Dear Luis,

    We are the customer with this problem, it still fail on low frequency, we modified N/MDAC divider value with 192k sample rate. It still fail on low frequency and high frequency fail, the result show below.

    And it also did 1k ohm and 4.7uF low-pass filter with output, did you test this solution before? it become more and more fail before we ask you.

    Did you have any solution that test success of 96k or 192k, please tell us.

    Thanks.

    AIC3204_cfg_192k.txt 
    ###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################


###############################################
# Clock Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.288 (48k) ~ 49.152 (192k) MHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NDAC = 1, MDAC = 2
w 30 0b 81 88
#
###############################################


###############################################
# Program the OSR of DAC to 32
###############################################
#
#
w 30 0d 00
w 30 0e 20
# w 30 0e 80
#
###############################################

###############################################
# Set the word length of Audio Interface to 
# 32bits PTM_P4
###############################################
#
#
w 30 1b 30
#
###############################################

###############################################
# Set the DAC Mode to PRB_P18 (filter type-C)
# (up to 192khz)
###############################################
#
#
w 30 3c 12
#
###############################################


###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# I2S to analog Setup
###############################################
# De-pop
w 30 14 25
#
# Set the Input Common Mode to 0.9V and Output 
# Common Mode for Headphone to Input Common Mode
w 30 0a 00
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Route LDAC/RDAC to LOL/LOR
w 30 0e 08 08
#
# Set the DAC PTM mode to PTM_P3/4
w 30 03 00 00
#
# Set the HPL/HPR gain to 0dB
w 30 10 00 00
#
# Set the LOL/LOR gain to 0dB
w 30 12 00 00
#
# Power up HPL/HPR and LOL/LOR drivers
w 30 09 3C
#
# Select Page 0
w 30 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
# power up DAC
w 30 3f d6
#
###############################################

  • 0 in reply to hong shihen
    TI__Guru* 84915 points
    Hi, Hong,

    Regarding the low-frequency level, could you reduce the output capacitance? The output capacitance generates a high-pass filter that reduces the low-frequency level. If the capacitor is reduced, the high-frequency pole will be moved and it will increase the low frequency content.

    Additionally, could you try with different processing blocks? Could you try with PRB_P17 or PRB_P19?

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 20 points

    Hi Luis,

    We try PRB_P17 and PRB_P19 process, It useful on PRB_P17 at low frequency, see below

    but PRB_P19 same as PRB_P18 before we use, see below

    and we also test lot of filter combination of cap and resistance at output, it didn't work on high frequency response. Do you have registers config that can fix it? or hardware solution?

    Thanks.

  • 0 in reply to hong shihen
    TI__Guru* 84915 points

    Hi, Hong,

    This could be related to the PLL and clock dividers settings. So, could you try the following things? 

    - We recommend to configure NDAC as large as possible. Could you try with different NDAC and MDAC values? (For example, NDAC = 4, MDAC = 2 or NDAC = 2, MDAC = 4, etc.).

    - If the problem persists, could you try using the PLL to get the sampling rate? Remember that the PLL conditions of app note must be followed ( http://www.ti.com/lit/ml/slaa557/slaa557.pdf#page=77 ).

    Best regards,
    Luis Fernando Rodríguez S.