Dear Sir,
Now I am able to interface 7825 with my controller.But problem is the counts i am getting is not right with mathematical calculations.
And I see counts not get saturated with Ref voltage.And i am getting full scale value as 32768 not 65536. I am unable to follow these things in data sheet also.
Need your support much.
Thanks
Radha
Hello Radha,
It is very good news that the interface is working.
As for the counts, they are in two’s complement format ranging from -32768 to 32767
This means that the input voltage is calculated from the output code as follows:
Vin = 8 * Vref / 65536 *CODE, where -32768 < CODE < 32767
Thus, Vref should be measured to calculate Vin, but if Vref were “exactly” 2.5V, this would be expected:
AnalogInput
Digital Output in Two's Complement Format
Binary CODE
HEX Code
9.999695V
0111 1111 1111 1111
7FFF
305.18uV
0000 0000 0000 0001
0001
0V
0000 0000 0000 0000
0000
-305.18uV
1111 1111 1111 1111
FFFF
-10.000000V
1000 0000 0000 0000
8000
I recommend using a “signed int” variable to store the data because its format is typically 16 bit two’s complement.
Let us know if this information helps.
Best Regards,
Rafael
Precision Data ConvertersApplications Team
Hello Rafael,
Thanks for your Input.. As per your reply I am getting my positive counts correctly. But In Negative I cant conclude whats happening..
I am doing 2's compliment
if( (AD_SDATA== 1) && Count ==0) //Negative polarity is setted then the following loop will execute { ADCOUNTSDATA = 0xFFFF - ADCOUNTSDATA; // 16 bit ADCOUNTSDATA is signed long. ADCOUNTSDATA = ADCOUNTSDATA * (-1); }
lcd_goto(8);sprintf(Buf,"%05Ld",ADCOUNTSDATA);
As per this for -9v I should get -25000 range but my display show 3000 counts only.Can U explain me what I should do.
and the Output 15 bits is not stable 50 counts is fluctuating. Can U help me further.
Thanks with Regards
Dear Rafael,
I have no reply from you so far, Any how now i have made my counts 14 bits only stable . I have found cross talk and channel interference in channel Input.
If i adjust my any one of my channel . The other channel counts get affected. Can u suggest me what to do?
Pl give me timely solution.
Regards
Hi Radha,
Are you still having trouble with the B2C number format? If so, please provide input voltage versus output codes and we'll take a look at that for you. On the noise, (crosstalk/count variation) can you provide a schematic of your ADS78925 interface to your applied input signal?
Regards,
Tom
Hi Tom,
Thanks for your reply .Here with I attach my schematic and my code for your reference3051.ads7825.pdf
I have selected external clock so I shorted R15 in my circuit.my Main issue is i got channel interference , means If i adjust 4th channel the 1st channel counts get affected by 10 to 20 counts.
If read only 3 channels .If i adjust 3 channel the same happens in 1 s6886.Tipper_ADC_REVe.ct channel. Its not matter with channel No, the order. pl check my code and circuit and give me timely solution.
Radha.P
What sort of input signals are you looking at? The INA126 is a little on the slow side and you may not be getting the input settled in time between MUX changes. What sampling rate are you using with the ADS7825?
My Input signal is from Load Cell. And I have also bypassed the INA126 and directly given to Analog Input of ADC.
My Sampling Rate is 200 SPS Only. I already attached m code and Schematic for your ref. Due to this Error I m unable
to implement in my project . Is is solvable ? Or Not.
Dear Tom,
I m waiting for your valuable reply.
Check the changes of the “ReadADCCounts” function in the attached text file.
1754.ReadADCCounts.c
It includes:
1) Changed “signed long” (32bits) to “signed int”(16bits) to have direct conversion to 2’s complement.
2) Clock is set idle LOW and R/C is set idle HIGH, and check that /BUSY isn't low.
3) 1us delay before and after channels pins are set.
4) The dummy conversion connects the selected channel to the internal sample and hold cap. (Loads the Address pin values)
5) Big delay (10us) before the actual conversion. This makes sure the sample and hold cap has the right voltage value before the good conversion starts.
6) Good conversion start and ends
7) SYNC is not tracked. Instead, a “balanced” 500KHz (2us period) dummy clock is used with idle low polarity.
8) The 16 good bits are read after the falling edge of the “balanced” 500KHz clock. At the 16th loop, clock should idle low.
9) Removed 2’s complement correction code. Since the variable is “signed int”(16bit), the 16 bits captured already represent decimal values in 2’s complement format(-32768to+32767)
As for hardware, a bridge sensor cannot be connected to the ADC inputs, the resistance from the sensor will affect performance. It needs to have the INA126 in between the ADC input and the bridge.
The schematic shows that there is an RC filter between the ADC input and INA126 output. Since the resistance can introduce errors, just connect the INA126 output directly(R=0) without a cap to the ADC input. If the un-averaged data is more the 5 counts peak-to-peak, the CAP might be need, but don't use it for now.
Let us know if the performance improves with any of these software and hardware recommendations.
Best regards,
Thanks for your input. Now Channel interference and crosstalk cleared. But seems to be little slower when took average samples.
Thank you for solving.