Could somebody confirm what is the correct data reading sequence from THS1206 ADC? If I understand the documentation correctly, the data read should be between two signals READ_ACTIVE and READ_INACTIVE. However, we observe a different scenario here. We only can read data AFTER the sequence READ_ACTIVE - READ_INACTIVE signals??? Tried to work with the timeouts of various signals, but still cannot figure out how this suppose to work. There is a TI document about this ADC, and it contains a picture that shows that output data are valid until next read strobe???
All signals (CLOCK, DATA_AV, READ/WRITE strobes) and times look very reasonable. ADC programming works OK also. Tests work, as expected (with the precision of the reading sequence). We are using non-TI ARM-based microcontroller. Trying to read 4 channels. FIFO depth 8
Any help is highly appreciated....
Hello One User,
Reading the data from the THS1206 actually involves three signals - the /RD (or RD/WR) input, the /CS0 input and the CS1 input. The two chip selects (active low /CS0 and active high CS1) control the data release on the bus. If these two signals are held static, the data bus will remain active and the last value on the bus will remain valid until the next conversion cycle completes (when DATA_AV goes active again). This is depicted in Figure 7 of the application note "Designing with the THS1206 High-Speed Data Converter" (document #SLAA094) . That diagram does not depict the chip select inputs, but you can refer to the THS1206 datasheet to see the required setup and hold times if you actively control these inputs. Please note, you don't have to actively control both chip select inputs - for instance, you could tie CS1 high and simply toggle /CS0 low to access the data.
The THS1206 can be configured to use a single RD/WR strobe or independent /RD and /WR inputs. If you have the device configured to use the single RD/WR input, you would need (at a minimum) to incorporate the /CS0 signal while trying to read data from the device - similar to Figure 36 on page 30 of the THS1206 datasheet. When configuring the device for FIFO level eight and four input channels, the DATA_AV interrupt output will signal when the FIFO has reached it's desired level. You would then simply read data eight times (2 conversion results for each input channel) by toggling the appropriate control lines. You need to read the complete FIFO contents before the next DATA_AV signal becomes active, if you do not, you will need to reset the FIFO to regain synchronization.
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