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Low frequency interference observed in ADS127L01EVM testing

John11513
Expert 5720 points
Other Parts Discussed in Thread: ADS127L01EVM, ADS127L01

Hi,

I observed some low frequency interference when testing ADS127L01EVM with shorted input.

The EVM is configured as default: OSR=32, filter is wide band 2, clk=16MHz, and is powered through USB. The differential input is shorted through J7-J9 and a short pieces of coaxial cable (~10cm).

Below is what I observed in GUI. You can find significant periodical spurs in time domain which results the ENOB (18.1) significantly lower than the datasheet result (18.84). What is the root cause of this periodical spurs?

Thank you,

John

  • 0
    TI__Guru 66446 points
    Hi John,

    The low frequency interference is the result of clock intermodulation between 2 on-board 16MHz oscillators. The period of the interference in your capture appears to be approximately 400Hz, which is likely the difference in the oscillator frequencies due to tolerance. You could analyze the frequency spectrum to confirm.

    We are working to address this with a revised EVM in the coming weeks.

    Best Regards,
  • 0 in reply to Ryan Andrews
    TI__Expert 5720 points

    Ryan,

    Yes, it is around 421Hz.

    Thank you,

    John

  • 0 in reply to John11513
    TI__Guru 66446 points
    Thanks, John.

    The easy fix is to depopulate Y1 and short the output of Y2 to the pad of Y1 where the output would be (pin 3). This will force both devices to run off of the same 16MHz oscillator. Note - the TIVA expects a 3.3V input, so use DVDD = 3.3V on the ADS127L01 (JP13 = [2-3]) if you want to try this.

    Again - this was an oversight on our part and will be corrected in the coming weeks with an update to the EVM.

    Best Regards,
  • 0 in reply to Ryan Andrews
    TI__Expert 5720 points

    Hi Ryan,

    I tried your proposal, the low frequency interference disappear. The ENOB increased from 18.1 to 18.3 (@500ksps, WB filter 2, HR mode), still cannot achieve the data spec. I tried connect Y2 to Y1 through coaxial cable with shield grounded at two and signle side. The single side grounding is the best. Below is the FFT result:

    Thank you,

    John

  • 0 in reply to John11513
    TI__Guru 66446 points
    Hi John,

    I'm glad this worked.

    The noise specs in the datasheet apply to DVDD = 1.8V. We see noise performance worsen slightly at higher digital supply levels, which is generally expected as the amplitudes of digital signals increase. Combined with an improved layout and clock distribution, the next EVM should get us closer to the device-level noise performance at 3.3V digital supply.

    If you have access to a dual-output function generator, you should be able to run the 'L01 off a 1.8-V clock while keeping the TIVA clock at 3.3V.

    Best Regards,
  • 0 in reply to Ryan Andrews
    TI__Expert 5720 points
    Thank you Ryan, I will try this latter.
  • 0 in reply to Ryan Andrews
    Prodigy 140 points
    Hi,

    I am a novice in the area of sigma-delta and high precision ADC. Any pointers would be helpful and appreciated.

    In my application I am recording the analogue output from a pressure transducer attached to a blood pressure cuff (assume 0V to 5V). The signals of interest are under 25 Hz. With the non-updated EVM, how many bits of usable data should I expect? How many more with the proposed updated EVM? The data rate I need currently is only 200 samples per second, but would like to increase to 1000 per second.

    Richard
  • 0 in reply to DoingNZ
    TI__Guru 66446 points
    Hi Richard,

    Especially at those data rates, I would expect you to get a lot closer to the datasheet noise performance, even with the EVM as-is today. The effective resolution is much closer to device-level performance vs. the noise-free resolution, since the latter is based on peak-to-peak noise. The noise-free resolution will improve significantly once the clock intermodulation tones are removed. As explained above, this can be realized with a quick bluewire modification if you're looking to get started right away.

    To achieve ~1kSPS, you would configure the device in Very-Low-Power Mode and use the Low-Latency filter with the highest oversampling ratio available, 2048. The -3dB bandwidth of the digital filter would be limited to < 1kHz, where the device can achieve >21.5 bits effective resolution.

    Let me know if you have further questions about this. I can take a measurement on the bench next week with the proposed changes to give you a better idea.

    Best Regards,