THS8200EP - Register setting for 1080P50/60 20bit 4:2:2

Our customer needs to fix their program today.

Could anybody help us on this question ?

Best Regards,

Kawai 

Unfortunately this is taking some time to check with the design team.

I will post an answer as soon as I can.

In the meantime I would suggest that 'working' settings be used.

BR,

Steve

OK, I think that there is a mistake in the example files.

Bit 7 should be '1', bit 6 should be '0' and bit 4 should be '0' I believe.

BR,

Steve

Steve-san,

Thank you for your great support.

As a result of confirming the designer, was the recommended register setting of address 0x03 = 0x81, for 1080p50/60 20bit 4:2:2 mode 148.5MHz ??

* Bit7 = 1 : DLL bypassed.

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I need to give the final answer to the customer.

I think the internal ciucuit cannot operate at 297MHz. DLL would be only available for CLKIN up to 80MHz.

Best Regards,

Kawai

OK, in section 4.3 of the datasheet it touches on this subject a little, but as you can see it is not actually very clear.

Here is the important part though...

"The user should not enable the 2x oversampling stage when the CLK_IN frequency exceeds 80 MHz, as
is the case for the higher PC graphics formats and 1080P HDTV. In this case the DLL should be bypassed
using the vesa_clk register to disable the 2x frequency generation. As explained in the detailed register
map description for this register, it is still possible to support 20-bit 4:2:2 input in this mode (for example,
for 1080P)."

The upshot is that bit 7 should = '1' (VESA_CLK), bit 6 should - '0' (DLL_BYPASS) and bit 4 should = '0' (FREQ_SEL)

Basically bit 6 = '1' means "ClkIn is 2x the data rate" which is NOT the case here, so disable all 2x processing.

BR,

Steve

Thank you very much Steve

Michael,

I have been experimenting a little with this and would like to correct myself.

I have found that bits 6 & 7 should actually always be the same in order to correctly bypass 2x internal processing and select correct clock sources.

For sampling frequencies above 80MHz I think it is necessary to set both bits 6 & 7, for sampling frequencies below 80MHz these bits should be clear.

Additionally, when bits 6 & 7 are set there is an additioanl 3 clock processing delay so depending on how you are configuring horizontal alignment you may need to change registers 0x79/0x7a by 3 counts.

Sorry for the confusion.

BR,

Steve

Steve-san,

Thank you very much for your support.

We have answered customer to use ADR 0x03 = 0xC1 at 1080p60/50 and now it is working.

But, there is another question referring the above setting.

ADR 0x03 bit6 is a bit used only in test mode. Can you guarantee the operation and electrical characteristics in the datasheet when setting this bit (ADR 0x03=0xC1)

Best Regards,

Kawai

I believe this is just bad wording in the datasheet. This CAN be used for test, but it is not limited to ONLY test.

BR,

Steve