CCS can access DDR2 ⇒ DDR2 good?

Hi,

I would like to ask a question about memory access.

I am debugging my customized OMAP L138 board which uses an external DDR2 memory. After configuring .GEL initialization according to parameters of my particular memory chip, which goes through the following steps:

1. Enable all PSCs.
2. Configures PLL0 and PLL1 for including ARM/DSP core and DDR2/mDDR controller.
3. Configure DDR2/mDDR controller with timing parameters of the memory including {CAS(CL) delay, tRFC, tRRD, etc.}

The change is summarized below:

I would like to know that from these facts, can I infer that

a)    I have already successfully configured the DDR2/mDDR controller of the OMAP L138 chip

b)    There is no board PCB routing defect and my DDR2 chip is now working

Should I be confident about a) and b) at this point?

Regarding the problem of loading program, I think I might still need to read some more about the dual-core architecture of the L138 chip; but I would like to if the assessments above can be made from such CCS interactions.

Thanks,

Zheng