am335x beaglebone + wl12xx

sodjas

Other Parts Discussed in Thread: WL1271, AM3354

Hi guys!

We're trying to connect WIFI + BT module: http://www.lsr.com/wireless-products/tiwi-r2

A hw partner connected it based on the general examples, at porting guides and as it was described in the board-am335xevm.c at the general purpose eves part.

The mmc and uart configration is the following (we connected it via mmc1 and uart1):

/* Module pin mux for wlan and bluetooth */
static struct pinmux_config mmc1_wl12xx_pin_mux[] = {
{"gpmc_ad8.mmc1_dat0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad10.mmc1_dat2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_ad11.mmc1_dat3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{NULL, 0},
};

static struct pinmux_config uart1_wl12xx_pin_mux[] = {
{"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
{"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
{"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
{NULL, 0},
};

We always get "wl12xx mmc device initialization failed" after setting platform data for wifi.

We don't have here any sophisticated daughter board but only connected WIFI to mmc and BT to uart.

Practically we altered the pinmux structs, enable gpios, and added init functions to cfg struct just as it is written in the porting guides but no success.

Could someone more experienced on this tell me how to start debugging the mmc init failed stuff.

Do wl12xx_set_platform_data needs to succeed in order to have a properly initialized device? Because for now I only see that it determines success based on if the .dev is not null.

I attached the complete board file. 4774.board-am335xevm.c

over 13 years ago

0 Naveen Jain over 13 years ago

TI__Intellectual 2480 points

Sodjas,

Can you also attach the kernel log during boot? I also suggest you to look at this post - http://e2e.ti.com/support/low_power_rf/f/307/t/219281.aspx - where I shared the code changes that I did and it works for me but you may have to change it based on your GPIO configuration.

Regarding the HW work - How are you connecting the BB with the Wi-Fi Module - are you connecting four SDIO_DATA, one SDIO_CMD, 1 SDIO_CLK, 1 WLAN_EN and 1 WLAN_IRQ line?
How you are providing the slow clock (32 KHz) and ref_clk and power to the module?

Regards,
Naveen

0 sodjas over 13 years ago in reply to Naveen Jain

Intellectual 830 points

Hi Naveen!

Thanks for the reply! In the meantime I made a small but important progress :)

I realised that the init function order in the dev_cfg struct is important for the mmc init function so if we want to use additional mmc interfaces like in our case there is an addditional init function BUT it must be placed before mmc0_init! Am I right? Because with the same file and this modification the mmc initialization works for me!

I'm also able to load the wl12xx_sdio.ko and netcfg shows wlan0 in interface list.

When I'm trying to bring up the interface I get:

wl1271: ERROR sdio write failed (-84)

but I found this thread http://e2e.ti.com/support/low_power_rf/f/307/t/181835.aspx and I think they solved the same problem.

So for now I'm fighting with this last step.

Thank you for the quick suport, I will come back with kernel log in a few minutes, just to try another boot.

Best Regards,

sodjas

0 sodjas over 13 years ago in reply to sodjas

Intellectual 830 points

So there is my kernel log

5315.kernel-log.rtf

0 sodjas over 13 years ago in reply to sodjas

Intellectual 830 points

HI,

Another info, I studied your linked forum post, downloaded the reference files and realized my stuff is pretty the same BUT :)

REF_CLOCK needs to be set to 26 HZ? and addition value the TCXCLOCK also needs to be set?

I'm asking just because no porting guide says OK this can vary from card to card :)

So wl12xx uses 26 HZ (actually I saw you wrote 24)?

Thanks, Best Regards,

sodjas

0 sodjas over 13 years ago in reply to sodjas

Intellectual 830 points

I'm replying myself several times :) but there is a progress again.

So the nasty stuff was a copy pasting but as I also pasted i2c2_init to dev_cfg but I dont need it, additionally it seems that is messed up things because its pinmuxing was also configured to uart1. So in short after removing it I got for net cfg wlan0 up:

[ 8255.485626] wl1271: firmware booted (Rev 6.3.6.0.79_2)
[ 8255.491027] wl1271: Driver version: R4_SP2_03_00
[ 8255.515350] ADDRCONF(NETDEV_UP): wlan0: link is not ready

What is the right output based on the porting guide.

Is this means that the mmc data lines the _en _irq and _clk stuff is all proper?

Last question is that the MAC is still the fake one 00:12:34:56:78:90. When this will be set? After the first calibration? How do I determine the mac address?

The porting guide says, that recalibration sets a random MAC and to say the desired MAC you want to set. I tought that this is platform's and driver's duty to set the real MAC stored in chip when wlan0 appears. How this works?

Best Regards,

sodjas

0 Naveen Jain over 13 years ago in reply to sodjas

TI__Intellectual 2480 points

Sodjas,

Look like you have covered a lot of ground over the weekend and made good progress. I will try to answer various questions that you have.

Regarding the mmc1_init to be before mmc0_init - I am not sure but I see that for most of the platforms the mmc1_init is before mmc0_init in dev_cfg so what you observed might be right.

Regarding the RefClck - http://processors.wiki.ti.com/index.php/OMAP35x_Wireless_Connectivity_Solution_Hardware#Clocks. Mostly we have modules with either 26 MHz or 38.4 MHz clock. Most of the Wl1271 module has 38.4 MHz clock. Please note that even if the clock is not set correctly, the firmware will still be downloaded and the interface will be us as it depends on SDIO clock, but the Wi-Fi operations like scan etc will not work.

wl1271: firmware booted (Rev 6.3.6.0.79_2) – This means that SDIO interface, and WLAN-EN is alright and firmware is loaded to the WL127x device. Are you able to perform ifconfig wlan0 up/down multiple times. Now after this if scan does not work – it might be either the WLAN_IRQ line is not mapped correctly for Wl12xx to wakeup host – so check that or the RefClk is not set correctly – Use 38.4 MHz.

MAC Address – The WLAN driver derives WLAN MAC addresses from the base address (BD_ADDR) read from the chip ROM at runtime if the MAC address field in the NVS file is set to an empty value (00:00:00:00:00:00). So, to use the MAC address assignment from ROM, we must set the empty MAC address 00:00:00:00:00:00 in the NVS file.

#calibrator set nvs_mac /lib/firmware/ti-connectivity/wl1271-nvs.bin 00:00:00:00:00:00

Regards,
Naveen

0 sodjas over 13 years ago in reply to Naveen Jain

Intellectual 830 points

Thank you very much Naveen!

Just another quick question :)

Where is the calibrator utility located?

Best Regards,

sodjas

0 Naveen Jain over 13 years ago in reply to sodjas

TI__Intellectual 2480 points

Sodjas,

The calibrator is located at git://github.com/TI-OpenLink/ti-utils.git

Regards,
Naveen

0 sodjas over 13 years ago in reply to Naveen Jain

Intellectual 830 points

Thank you very much!

Teh ref clock set to 38.4 MHz made the magic :)

I currently successfully scanning visible wlan's.

Thanks again!

Really appreciate!

Best Regards,

sodjas

0 Andrew Glen over 12 years ago in reply to sodjas

Prodigy 160 points

Hello Sodjas,

I am just working on bringing up a new Beaglebone based board with the same TiWi-R2 chip you successfully got going. I'm not quite at the stage of bringing up the wifi, but I was wondering if you could share your final 'board-am335xevm.c' file and point out any additional changes or tweaks you made to get it to work.

It all sounds like it should be fine, but I want to reduce the number of unknowns as much as possible before I start debugging my hardware!

Cheers,

Andrew Glen.

0 sodjas over 12 years ago in reply to Andrew Glen

Intellectual 830 points

Hi Andrew,

attached the board and mux file. Mux file is only interesting if you have some signal defs that are not defined by default and you want to use them. In my case it is the uart4 if you diff the file with the original one you will see what I'm talking about.

hope it helps!

8867.board-am335xevm.c

Fullscreen 7848.mux33xx.c Download

/*
 * AM33XX mux data
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
 *
 * Copyright (C) 2009 Nokia
 * Copyright (C) 2009 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>

#include "mux.h"

#ifdef CONFIG_OMAP_MUX

#define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
{									\
	.reg_offset	= (AM33XX_CONTROL_PADCONF_##M0##_OFFSET),	\
	.gpio		= (g),						\
	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
}

/* AM33XX pin mux super set */
static struct omap_mux __initdata am33xx_muxmodes[] = {
	_AM33XX_MUXENTRY(GPMC_AD0, 0,
		"gpmc_ad0", "mmc1_dat0", NULL, NULL,
		NULL, NULL, NULL, "gpio1_0"),
	_AM33XX_MUXENTRY(GPMC_AD1, 0,
		"gpmc_ad1", "mmc1_dat1", NULL, NULL,
		NULL, NULL, NULL, "gpio1_1"),
	_AM33XX_MUXENTRY(GPMC_AD2, 0,
		"gpmc_ad2", "mmc1_dat2", NULL, NULL,
		NULL, NULL, NULL, "gpio1_2"),
	_AM33XX_MUXENTRY(GPMC_AD3, 0,
		"gpmc_ad3", "mmc1_dat3", NULL, NULL,
		NULL, NULL, NULL, "gpio1_3"),
	_AM33XX_MUXENTRY(GPMC_AD4, 0,
		"gpmc_ad4", "mmc1_dat4", NULL, NULL,
		NULL, NULL, NULL, "gpio1_4"),
	_AM33XX_MUXENTRY(GPMC_AD5, 0,
		"gpmc_ad5", "mmc1_dat5", NULL, NULL,
		NULL, NULL, NULL, "gpio1_5"),
	_AM33XX_MUXENTRY(GPMC_AD6, 0,
		"gpmc_ad6", "mmc1_dat6", NULL, NULL,
		NULL, NULL, NULL, "gpio1_6"),
	_AM33XX_MUXENTRY(GPMC_AD7, 0,
		"gpmc_ad7", "mmc1_dat7", NULL, NULL,
		NULL, NULL, NULL, "gpio1_7"),
	_AM33XX_MUXENTRY(GPMC_AD8, 0,
		"gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
		NULL, NULL, NULL, "gpio0_22"),
	_AM33XX_MUXENTRY(GPMC_AD9, 0,
		"gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
		"ehrpwm2B", NULL, NULL, "gpio0_23"),
	_AM33XX_MUXENTRY(GPMC_AD10, 0,
		"gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
		NULL, NULL, NULL, "gpio0_26"),
	_AM33XX_MUXENTRY(GPMC_AD11, 0,
		"gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
		NULL, NULL, NULL, "gpio0_27"),
	_AM33XX_MUXENTRY(GPMC_AD12, 0,
		"gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
		NULL, NULL, NULL, "gpio1_12"),
	_AM33XX_MUXENTRY(GPMC_AD13, 0,
		"gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
		NULL, NULL, NULL, "gpio1_13"),
	_AM33XX_MUXENTRY(GPMC_AD14, 0,
		"gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
		NULL, NULL, NULL, "gpio1_14"),
	_AM33XX_MUXENTRY(GPMC_AD15, 0,
		"gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
		NULL, NULL, NULL, "gpio1_15"),
	_AM33XX_MUXENTRY(GPMC_A0, 0,
		"gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
		NULL, NULL, NULL, "gpio1_16"),
	_AM33XX_MUXENTRY(GPMC_A1, 0,
		"gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
		NULL, NULL, NULL, "gpio1_17"),
	_AM33XX_MUXENTRY(GPMC_A2, 0,
		"gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
		NULL, NULL, NULL, "gpio1_18"),
	_AM33XX_MUXENTRY(GPMC_A3, 0,
		"gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
		NULL, NULL, NULL, "gpio1_19"),
	_AM33XX_MUXENTRY(GPMC_A4, 0,
		"gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
		"gpmc_a20", NULL, NULL, "gpio1_20"),
	_AM33XX_MUXENTRY(GPMC_A5, 0,
		"gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
		"gpmc_a21", NULL, NULL, "gpio1_21"),
	_AM33XX_MUXENTRY(GPMC_A6, 0,
		"gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
		"gpmc_a22", NULL, NULL, "gpio1_22"),
	_AM33XX_MUXENTRY(GPMC_A7, 0,
		"gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
		NULL, NULL, NULL, "gpio1_23"),
	_AM33XX_MUXENTRY(GPMC_A8, 0,
		"gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
		NULL, NULL, "mcasp0_aclkx", "gpio1_24"),
	_AM33XX_MUXENTRY(GPMC_A9, 0,
		"gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
		NULL, NULL, "mcasp0_fsx", "gpio1_25"),
	_AM33XX_MUXENTRY(GPMC_A10, 0,
		"gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
		NULL, NULL, "mcasp0_axr0", "gpio1_26"),
	_AM33XX_MUXENTRY(GPMC_A11, 0,
		"gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
		NULL, NULL, "mcasp0_axr1", "gpio1_27"),
	_AM33XX_MUXENTRY(GPMC_WAIT0, 0,
        "gpmc_wait0", "mii2_crs", "gpmc_csn4", "rmii2_crs_dv",
        "mmc1_sdcd", NULL, "uart4_rxd_mux2", "gpio0_30"),
	_AM33XX_MUXENTRY(GPMC_WPN, 0,
        "gpmc_wpn", "mii2_rxerr", "gpmc_csn5", "rmii2_rxerr",
        "mmc2_sdcd", NULL, "uart4_txd_mux2", "gpio0_31"),
	_AM33XX_MUXENTRY(GPMC_BEN1, 0,
		"gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
		NULL, NULL, "mcasp0_aclkr", "gpio1_28"),
	_AM33XX_MUXENTRY(GPMC_CSN0, 0,
		"gpmc_csn0", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio1_29"),
	_AM33XX_MUXENTRY(GPMC_CSN1, 0,
		"gpmc_csn1", NULL, "mmc1_clk", NULL,
		NULL, NULL, NULL, "gpio1_30"),
	_AM33XX_MUXENTRY(GPMC_CSN2, 0,
		"gpmc_csn2", NULL, "mmc1_cmd", NULL,
		NULL, NULL, NULL, "gpio1_31"),
	_AM33XX_MUXENTRY(GPMC_CSN3, 0,
		"gpmc_csn3", NULL, NULL, "mmc2_cmd",
		NULL, NULL, NULL, "gpio2_0"),
	_AM33XX_MUXENTRY(GPMC_CLK, 0,
		"gpmc_clk", "lcd_memory_clk_mux", NULL, "mmc2_clk",
		NULL, NULL, "mcasp0_fsr", "gpio2_1"),
	_AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
		"gpmc_advn_ale", NULL, NULL, NULL,
		NULL, NULL, NULL, "mmc1_sdcd"),
	_AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
		"gpmc_oen_ren", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_3"),
	_AM33XX_MUXENTRY(GPMC_WEN, 0,
		"gpmc_wen", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_4"),
	_AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
		"gpmc_ben0_cle", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_5"),
	_AM33XX_MUXENTRY(LCD_DATA0, 0,
		"lcd_data0", "gpmc_a0", NULL, NULL,
		NULL, NULL, NULL, "gpio2_6"),
	_AM33XX_MUXENTRY(LCD_DATA1, 0,
		"lcd_data1", "gpmc_a1", NULL, NULL,
		NULL, NULL, NULL, "gpio2_7"),
	_AM33XX_MUXENTRY(LCD_DATA2, 0,
		"lcd_data2", "gpmc_a2", NULL, NULL,
		NULL, NULL, NULL, "gpio2_8"),
	_AM33XX_MUXENTRY(LCD_DATA3, 0,
		"lcd_data3", "gpmc_a3", NULL, NULL,
		NULL, NULL, NULL, "gpio2_9"),
	_AM33XX_MUXENTRY(LCD_DATA4, 0,
		"lcd_data4", "gpmc_a4", NULL, NULL,
		NULL, NULL, NULL, "gpio2_10"),
	_AM33XX_MUXENTRY(LCD_DATA5, 0,
		"lcd_data5", "gpmc_a5", NULL, NULL,
		NULL, NULL, NULL, "gpio2_11"),
	_AM33XX_MUXENTRY(LCD_DATA6, 0,
		"lcd_data6", "gpmc_a6", NULL, NULL,
		NULL, NULL, NULL, "gpio2_12"),
	_AM33XX_MUXENTRY(LCD_DATA7, 0,
		"lcd_data7", "gpmc_a7", NULL, NULL,
		NULL, NULL, NULL, "gpio2_13"),
	_AM33XX_MUXENTRY(LCD_DATA8, 0,
		"lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
		NULL, NULL, "uart2_ctsn", "gpio2_14"),
	_AM33XX_MUXENTRY(LCD_DATA9, 0,
		"lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
		NULL, NULL, "uart2_rtsn", "gpio2_15"),
	_AM33XX_MUXENTRY(LCD_DATA10, 0,
		"lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
		NULL, NULL, NULL, "gpio2_16"),
	_AM33XX_MUXENTRY(LCD_DATA11, 0,
		"lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
		"mcasp0_axr2", NULL, NULL, "gpio2_17"),
	_AM33XX_MUXENTRY(LCD_DATA12, 0,
		"lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
		"mcasp0_axr2", NULL, NULL, "gpio0_8"),
	_AM33XX_MUXENTRY(LCD_DATA13, 0,
		"lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
		"mcasp0_axr3", NULL, NULL, "gpio0_9"),
	_AM33XX_MUXENTRY(LCD_DATA14, 0,
		"lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
		NULL, NULL, NULL, "gpio0_10"),
	_AM33XX_MUXENTRY(LCD_DATA15, 0,
		"lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
		"mcasp0_axr3", NULL, NULL, "gpio0_11"),
	_AM33XX_MUXENTRY(LCD_VSYNC, 0,
		"lcd_vsync", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_22"),
	_AM33XX_MUXENTRY(LCD_HSYNC, 0,
		"lcd_hsync", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_23"),
	_AM33XX_MUXENTRY(LCD_PCLK, 0,
		"lcd_pclk", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_24"),
	_AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
		"lcd_ac_bias_en", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_25"),
	_AM33XX_MUXENTRY(MMC0_DAT3, 0,
		"mmc0_dat3", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_26"),
	_AM33XX_MUXENTRY(MMC0_DAT2, 0,
		"mmc0_dat2", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_27"),
	_AM33XX_MUXENTRY(MMC0_DAT1, 0,
		"mmc0_dat1", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_28"),
	_AM33XX_MUXENTRY(MMC0_DAT0, 0,
		"mmc0_dat0", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_29"),
	_AM33XX_MUXENTRY(MMC0_CLK, 0,
		"mmc0_clk", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_30"),
	_AM33XX_MUXENTRY(MMC0_CMD, 0,
		"mmc0_cmd", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio2_31"),
	_AM33XX_MUXENTRY(MII1_COL, 0,
		"mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
		"mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
	_AM33XX_MUXENTRY(MII1_CRS, 0,
		"mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
		"mcasp1_aclkx", NULL, NULL, "gpio3_1"),
	_AM33XX_MUXENTRY(MII1_RXERR, 0,
		"mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
		"mcasp1_fsx", NULL, NULL, "gpio3_2"),
	_AM33XX_MUXENTRY(MII1_TXEN, 0,
		"mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
		"mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
	_AM33XX_MUXENTRY(MII1_RXDV, 0,
		"mii1_rxdv", NULL, "rgmii1_rctl", NULL,
		"mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
	_AM33XX_MUXENTRY(MII1_TXD3, 0,
		"mii1_txd3", NULL, "rgmii1_td3", NULL,
		"mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
	_AM33XX_MUXENTRY(MII1_TXD2, 0,
		"mii1_txd2", NULL, "rgmii1_td2", NULL,
		"mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
	_AM33XX_MUXENTRY(MII1_TXD1, 0,
		"mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
		"mcasp1_axr1", NULL, "mmc1_cmd", "gpio0_21"),
	_AM33XX_MUXENTRY(MII1_TXD0, 0,
		"mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
		"mcasp1_aclkr", NULL, "mmc1_clk", "gpio0_28"),
	_AM33XX_MUXENTRY(MII1_TXCLK, 0,
		"mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
		"mmc1_dat0", NULL, "mcasp0_aclkx", "gpio3_9"),
	_AM33XX_MUXENTRY(MII1_RXCLK, 0,
		"mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
		"mmc1_dat1", NULL, "mcasp0_fsx", "gpio3_10"),
	_AM33XX_MUXENTRY(MII1_RXD3, 0,
		"mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
		"mmc1_dat2", NULL, "mcasp0_axr0", "gpio2_18"),
	_AM33XX_MUXENTRY(MII1_RXD2, 0,
		"mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
		"mmc1_dat3", NULL, "mcasp0_axr1", "gpio2_19"),
	_AM33XX_MUXENTRY(MII1_RXD1, 0,
		"mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
		"mcasp1_fsr", NULL, "mmc2_clk", "gpio2_20"),
	_AM33XX_MUXENTRY(MII1_RXD0, 0,
		"mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
		"mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
	_AM33XX_MUXENTRY(MII1_REFCLK, 0,
		"rmii1_refclk", NULL, "spi1_cs0", NULL,
		"mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
	_AM33XX_MUXENTRY(MDIO_DATA, 0,
		"mdio_data", NULL, NULL, NULL,
		"mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
	_AM33XX_MUXENTRY(MDIO_CLK, 0,
		"mdio_clk", NULL, NULL, NULL,
		"mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
	_AM33XX_MUXENTRY(SPI0_SCLK, 0,
		"spi0_sclk", "uart2_rxd", "i2c2_sda", NULL,
		NULL, NULL, NULL, "gpio0_2"),
	_AM33XX_MUXENTRY(SPI0_D0, 0,
		"spi0_d0", "uart2_txd", "i2c2_scl", NULL,
		NULL, NULL, NULL, "gpio0_3"),
	_AM33XX_MUXENTRY(SPI0_D1, 0,
		"spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
		NULL, NULL, NULL, "gpio0_4"),
	_AM33XX_MUXENTRY(SPI0_CS0, 0,
		"spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
		NULL, NULL, NULL, "gpio0_5"),
	_AM33XX_MUXENTRY(SPI0_CS1, 0,
		"spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
		NULL, "mmc0_sdcd", NULL, "gpio0_6"),
	_AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
		"ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
		"spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
	_AM33XX_MUXENTRY(UART0_CTSN, 0,
		"uart0_ctsn", NULL, "d_can1_tx", "i2c1_sda",
		"spi1_d0", NULL, NULL, "gpio1_8"),
	_AM33XX_MUXENTRY(UART0_RTSN, 0,
		"uart0_rtsn", NULL, "d_can1_rx", "i2c1_scl",
		"spi1_d1", "spi1_cs0", NULL, "gpio1_9"),
	_AM33XX_MUXENTRY(UART0_RXD, 0,
		"uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
		NULL, NULL, NULL, "gpio1_10"),
	_AM33XX_MUXENTRY(UART0_TXD, 0,
		"uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
		NULL, NULL, NULL, "gpio1_11"),
	_AM33XX_MUXENTRY(UART1_CTSN, 0,
		"uart1_ctsn", NULL, NULL, "i2c2_sda",
		"spi1_cs0", NULL, NULL, "gpio0_12"),
	_AM33XX_MUXENTRY(UART1_RTSN, 0,
		"uart1_rtsn", NULL, NULL, "i2c2_scl",
		"spi1_cs1", NULL, NULL, "gpio0_13"),
	_AM33XX_MUXENTRY(UART1_RXD, 0,
		"uart1_rxd", "mmc1_sdwp", NULL, "i2c1_sda",
		NULL, "pr1_uart0_rxd_mux1", NULL, "gpio0_14"),
	_AM33XX_MUXENTRY(UART1_TXD, 0,
		"uart1_txd", "mmc2_sdwp", NULL, "i2c1_scl",
		NULL, "pr1_uart0_txd_mux1", NULL, "gpio0_15"),
	_AM33XX_MUXENTRY(I2C0_SDA, 0,
		"i2c0_sda", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio3_5"),
	_AM33XX_MUXENTRY(I2C0_SCL, 0,
		"i2c0_scl", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio3_6"),
	_AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
		"mcasp0_aclkx", NULL, NULL, "spi1_sclk",
		"mmc0_sdcd", NULL, NULL, "gpio3_14"),
	_AM33XX_MUXENTRY(MCASP0_FSX, 0,
		"mcasp0_fsx", NULL, NULL, "spi1_d0",
		"mmc1_sdcd", NULL, NULL, "gpio3_15"),
	_AM33XX_MUXENTRY(MCASP0_AXR0, 0,
		"mcasp0_axr0", NULL, NULL, "spi1_d1",
		"mmc2_sdcd", NULL, NULL, "gpio3_16"),
	_AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
		"mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
		NULL, NULL, NULL, "gpio3_17"),
	_AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
		"mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
		"mmc0_sdwp", NULL, NULL, "gpio3_18"),
	_AM33XX_MUXENTRY(MCASP0_FSR, 0,
		"mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
		NULL, "pr1_pru0_pru_r30_5", NULL, "gpio3_19"),
	_AM33XX_MUXENTRY(MCASP0_AXR1, 0,
		"mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
		NULL, NULL, NULL, "gpio3_20"),
	_AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
		"mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
		NULL, NULL, NULL, "gpio3_21"),
	_AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
		"xdma_event_intr0", NULL, NULL, NULL,
		"spi1_cs1", NULL, NULL, "gpio0_19"),
	_AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
		"xdma_event_intr1", NULL, NULL, "clkout2",
		NULL, NULL, NULL, "gpio0_20"),
	_AM33XX_MUXENTRY(WARMRSTN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(PWRONRSTN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(NMIN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(XTALIN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(XTALOUT, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(TMS, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(TDI, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(TDO, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(TCK, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(TRSTN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(EMU0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio3_7"),
	_AM33XX_MUXENTRY(EMU1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio3_8"),
	_AM33XX_MUXENTRY(RTC_XTALIN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(RTC_XTALOUT, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(EXT_WAKEUP, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
		"usb0_drvvbus", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio0_18"),
	_AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
		"usb1_drvvbus", NULL, NULL, NULL,
		NULL, NULL, NULL, "gpio3_13"),
	_AM33XX_MUXENTRY(DDR_RESETN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_CSN0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_CKE, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_CK, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_CKN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_CASN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_RASN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_WEN, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_BA0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_BA1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_BA2, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A2, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A3, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A4, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A5, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A6, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A7, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A8, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A9, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A10, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A11, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A12, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A13, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A14, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_A15, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_ODT, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D2, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D3, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D4, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D5, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D6, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D7, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D8, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D9, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D10, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D11, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D12, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D13, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D14, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_D15, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_DQM0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_DQM1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_DQS0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_DQSN0, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_DQS1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_DQSN1, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_VREF, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(DDR_VTP, 0,
		NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(AIN0, 0,
		"ain0", NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(AIN1, 0,
		"ain1", NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(AIN2, 0,
		"ain2", NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(AIN3, 0,
		"ain3", NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(VREFP, 0,
		"vrefp", NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	_AM33XX_MUXENTRY(VREFN, 0,
		"vrefn", NULL, NULL, NULL,
		NULL, NULL, NULL, NULL),
	{ .reg_offset = OMAP_MUX_TERMINATOR },
};

int __init am33xx_mux_init(struct omap_board_mux *board_subset)
{
	return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
			AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
			NULL, board_subset, NULL);
}
#else
int __init am33xx_mux_init(struct omap_board_mux *board_subset)
{
	return 0;
}
#endif

best regards,

sodjas

0 Andrew Glen over 12 years ago in reply to sodjas

Prodigy 160 points

Thanks sodjas, that is a massive help!

0 Andrew Glen over 12 years ago in reply to sodjas

Prodigy 160 points

Hi Sodjas,

With help from your board file I was able to get the MMC working and the wifi chip is now detected.

I have one additional question if you don't mind: What process did you use to compile the wl12xx drivers? I've been trying with a combination of building them into the kernel, using compat-wireless, using various other suggestions from TI, but nothing seems to work completely. Basically what is happening is that I can't get a complete set of compatible .ko files. How did you go about doing this, I'm a bit mystified?

Cheers,

Andrew.

0 sodjas over 12 years ago in reply to Andrew Glen

Intellectual 830 points

Hi Andrew,

Glad to hear good news.

We simply put the

$(call inherit-product-if-exists, hardware/ti/wlan/mac80211/firmware/wl12xx_wlan_fw_products.mk)

$(call inherit-product-if-exists, hardware/ti/wpan/wl12xx-bluetooth/wl12xx_bt_products.mk)

lines in our device.mk which triggers the custom build of ko-s at /hardware/ti/wlan...

This should work on ICS, I suggest you at first boot to play with the command line test verification which is described here:

2.6 Verify WLAN from console

If these commands succeed I think you will already see available wlan on the ui as well, if everything is good but scan fails then you need to play with ref_clock, but if you have the same tipi_r2 the ref_clock configured in my board file should do the trick.

After this there is still one step to get a valid mac, not the 00:12:34... or similar. This is the:

2.7 WLAN calibration

Autocalibrate is not a good option as if you have multiple devices it will configure the same mac for all.

We don't use the ethernet in our project so we managed to set ethernet mac for WIFI.

WIFI turned out to be very exotic here, because for us it is prefectly working on ICS but we had some MMC read/write problems with it on JB, some TI employees told me that the code and scripts in the repo are updated very often so I hope we will have this up and working on JB too, which is awesome compared to ICS but don't have WIFI in our case so we stick to ICS for some time.

Hope this helps,

Best regards,

sodjas

0 Andrew Glen over 12 years ago in reply to sodjas

Prodigy 160 points

Hi Sodjas,

Thanks for that - you should have your own TI wiki page! I should have mentioned that I'm working with the Angstrom distribution so things will be a bit different. I think my problem is that I haven't completely abandoned building the drivers using compat-wireless. I used compat-wireless initially for our proof of concept which just used a beaglebone and an ath9k_htc usb-wifi stick - for some reason I could get the ath9k drivers to build and run no problem, but the ti wl12xx one's don't seem to get built for reasons I do not understand. I think I need to do a bit of cleaning out and keep all the wifi drivers entirely 'native within angstrom'. I might even have everything sitting there on my build machine already. After spending a few hours going around in circles it can become hard to see the woods for the trees!!

Thanks for your help - this is my first time working on open-source software, and it's awesome to have people out there willing to lend a hand!

Andrew.

0 Andrew Glen over 12 years ago in reply to Andrew Glen

Prodigy 160 points

Hi Sodjas,

Sorry for such a delay between message. I was never able to get the tiwi-r2 to work and then got distracted by some other work, but am now back into it. I was hoping you might be able to give some more advice.

I am interfacing the am3354 the tiwi-r2 over sdio directly (i.e. with in intermediate voltage translation chips), so I have powered the voltage inputs with 1.8V in order to run everything at the same voltage. All of the working examples of the AM335x/tiwi-r2 interfacing appear to use intermediate voltage translation chips (from 3V3 on the am335x to 1V8 on the tiwi-r2), so I'm wondering if this point of difference is why my own design doesn't work.

So, did you use voltage translation chips on your design? Or did it all work successfully with everything a 1V8?

If you did get it all to work at 1.8V with no intermediate chips I'd be very interested in hearing more about your hardware design, to see where and how it differs from my own...

At this stage I'm planning on making a new design that exactly matches the 'known good' reference design I have with the beaglebone/wifi cape - but I'd very much like to avoid this if possible!!

Regards,

Andrew.

0 sodjas over 12 years ago in reply to Andrew Glen

Intellectual 830 points

Hi Andrew,

Unfortunately I'm a sotfware guy, the expansion hw design was outsourced, but you thought right. The electrician guys who made the expansion knew nothing personal about the beaglebone, they just had the SRM and mainly used it to study the expansion pinout.

ALL other they did, they did it how the recommendations are written, so YES they used voltage translator. I remember the guy told me that he is waiting for it because the voltage coming from the bone should be translated.

So with my software development side of view I only could say you to follow the conventions written in reference docs and it should work :)

Hope this helps,

br sodjas

0 Andrew Glen over 12 years ago in reply to sodjas

Prodigy 160 points

Hi Sodjas,

Thank you for your response. I too am just a software guy, so I've been really scratching my head on this one. It is good to know you did use voltage translation chips - at this point, regardless of the fact that it should in theory work without them if the power supplies are setup correctly, every reference I have heard to someone using the tiwi-r2 with an am335x has involved voltage translation chips. We don't have them, our design doesn't work, so I'm going to stop making things up in software and get a new hardware revision made.

Thanks for your help.

Andrew.

0 John Murphy1 over 12 years ago in reply to Andrew Glen

Expert 1210 points

I have bought the BeagleBone WiFi/BT cape. The WiFi works fine with the Linux (v3.2) distro supplied by CircuitCo. [But the BT doesn't work.]

Since it comes with working schematics & Linux source, it would be a good reference for you.

0 Andrew Glen over 12 years ago in reply to John Murphy1

Prodigy 160 points

Hi John,

Yeah, we did use the Beaglebone+Wifi Cape as our starting reference, and have been able to prove our software design with this setup. We then decided to be 'smart' and run the SDIO at 1.8V from the main processor on our own custom board, negating the need for intermediate voltage translation chips between the AM335x and the Tiwi-R2 ,which were (apparently) only required because the power feeds to the processor on the beaglebone are hardwired with 3.3V - but we have been unable to get this to work, and we have been unable to find anyone else who has succeeded with this configuration, or to confirm whether it should/shoudn't work.

So as you suggested, we are in the process of duplicating the beaglebone/wifi circuitry on an new board spin with all of the additional circuitry that this entails.

Regards,

Andrew.

0 VICTOR LEITE over 11 years ago in reply to Andrew Glen

Intellectual 550 points

Hi Sodjas,

I was on the same situation. After 3 weeks going through the wrong direction, I've read your post and got my problem solved in two days. I would never think the problem was on the board file. I didn't see any of the TI experts assuming this possibility. Also I didn't have many replies on my questions. Perhaps after lots of time figuring out the gaps on TI wiki, rebuilding drivers, kernels, revising all the hardware project again, etc etc etc I would think of it.

I had my board file totally cleaned for wifi operation and this got it working properly. Probably, mmc0 / mmc1 init order as you said or maybe overlapping of pinmux configuration. Now I'm going to add the rest of the code again, step by step to figure out what exactly was messing things up.

Thank you very much for sharing your experience!

0 sodjas over 11 years ago in reply to VICTOR LEITE

Intellectual 830 points

Hey Victor!

Glad to hear these kind of good news! Keep up with the good work!

Best Regards,

sodjas

Wi-Fi

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am335x beaglebone + wl12xx