F28235 ADC dual-sequencer SEQ2 timing problem

Kaixin,

I did look over your code from the other thread carefully, but I am not able to determine why you are seeing this behavior.  Were you able to make any progress?

Another question is how to use ADCCLKPS and ADCCLK?

My HSPCLK=25MHz, When I use the default settings, ACCLKPS=ADCCLK=0, ACQ_PS=0, it works OK.  But when I set  ACCLKPS=2, ADCCLK=1, and do 8 seq reading, the first 4 results are all 0, and the timings are also weird.

I am going to have the same test on the 28335 demo board later. 

Hi Kaixin,

Did you go through this doc??

3582.ADC_28335.pdf

All your doubts would vanish after reading this pdf.

Regards,

Gautam

  Hi,

 I have read through these reference guides many times but the result was not as I expected...

 Best regards,

Kaixin 

Very strange! I hope a TI employee solves your issue.

Regards,

Gautam 

one more question, AdcRegs.ADCST.all is not consistent with AdcRegs.ADCST.bit.SEQ1_BSY.

see the following code clip...

AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;    // start conversion

adc_st = AdcRegs.ADCST.all;                    // make copy of ADCST

adc_busy1=AdcRegs.ADCST.bit.SEQ1_BSY;  // make copy of bit.SEQ1_BSY

Result:

adc_st = 0

adc_busy1=1

why??

Hi Kaixin,

The results seem to be fine! What is "not consistent"?

Regards,

Gautam

Guatam,

I think the issue is that when using the .bit to read, Kaixin gets one value, but when using the .all, another value is produced.  These should correspond to the same region in memory.  

Kaixin,

I wonder if it takes a few cycles for this bit to get set.  Can you try doing the reads in a different order, doing the same read multiple times in a row, and/or adding NOPs before the first read?