epi

Hi Arye!

EPI is associated with M3 core only. ControlSuite has some examples for using EPI with SDRAM. Could you please explain your question in more details? What do you mean under "write/read to the Local"?

Regards,

Igor 

Hello Igor:

In Ver. B of the concerto you can access the epi also from the c28. You can write to the epi from the c28 . So my question is what happens if the M3 writes or reads and the c28 does the same? or am I missing something.

Regards Arye

Hi!

I'm sorry. I'm behind the times. You are right (Silicon Errata SPRZ357F). But at the same time it seems the new TRM does not  highlight the problem of EPI sharing. And TI employees are silent still...

Regards,

Igor

Hello Igor:

Any updates regarding my question?

regards Arye

Hi Arye!

I attempted to draw the attention of TI employees to this issue but so far without success. Thus in information isolation conditions let's try to go on another way. Do you really wish to use EPI like shared resource? If NOT, then it seems you should not think about this issue. But if YES, then in my opinion you need to think about writing critical section (flags, semaphores etc.) It is all at now...

Regards,

Igor 

Unfortunately I do not know how the EPI to C28x was implemented.  Our EPI expert is on travel, but folks are looking into this during his absence.

Hello Lori!

Many thanks. We will wait new info.

Regards,

Igor

Hello Lori and Igor:

First I'd like to thank you for the help. Next I have another question regarding the epi.

I configured the epi to HB16 with two Chip Selects. Some how when I look at the Chip selects I see both of them go low instead of one to go low on one set of addresses and the second to go low on another set of addresses like described in spruh22e pg 1382.

Regards Arye

Hello Arye!

I'm sorry. Perhaps I have some language problem. Do you mean Dual-Chip-Select mode? Could you please explain your above qustion more clearly or in more details?

Regards,

Igor

Hello Arye!

Have you similar problem like this http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/285294.aspx?

Regards,

Igor

Hello Igor:

The situation is like that. The two Chip Selects go Low together. Although each Chip select should go low when I access the address it is configured to go Low.

The other problem is similar to what you sent me but the situation is different. In Rev 0 the ALE is LOW and goes HIGH when you access the bus but in REV B it is inverted is this the case or there is a different configuration in Rev B.

Regards Arye

Hello Arye!

Certainly I'm worse than you into understanding EPI still (50 pages of "TRM Chapter 19" it's enough to break down the brain). Maybe my questions are useless in your opinion. But at first for my understanding.

1 Did you go through 19.5 carefully?

2 What mode are you going to apply : (SDRAM) mode, Traditional Host-Bus mode or General-Purpose mode?

If you find our communication unproductive then you can no answer.

Regards,

Igor 

Hello Igor:

Yes I went through 19.5. I'm using the HB16 configuratin with data and address multilexed and dual chip select.

Regards Arye

Hello Arye!

Thanks for answers. Now let's go to 19.8.10.  If I understand you set CSCFG=0x2 (or 0x3) in the EPIHBnCFG2 register. But now it all depends on setting fields EPADR & ERADR. There are three variants:

1) EPADR is not 0x0 &  ERADR is 0x0; EPADR is used for both chip selects

2) EPADR 0x0 &  ERADR is not 0x0; ERADR is used for both chip selects

3) EPADR is not 0x0 &  ERADR is not 0x0; EPADR for CSn0 & ERADR for CSn1

What is your variant?

Regards,

Igor

Hello Igor:

I use CSCFG = 0x3.  Telling you the truth I've tried all three combination and all three the same result. Both Chip selects go Low. You can try on an evaluation board and look on the scope that two CS go low. If you can find any body that uses two CS and it works for him I'd be glad to find the secret and what am I doing wrong.

Thank you in advance Arye

Hello Arye!

I have no doubt on the objectivity of your information and results. But if you are not tired so far, could you please to describe in details your settings for EPIHB16CFG & EPIHB16CFG2?

Also I have noticed in Table 19-14 (p. 1380) that for CSCFG the value 0x3 is absent (VALUE column) which corresponds " ALE with Dual CSn Configuration". Well probably this is typo.

Regards,

Igor

Hello Vivek:

Thank you very much for the answer.

Would you be able to knoe if the ALE signal is inverted in Rev B from Rev 0 of the concerto. I see in Rev 0 ALE LOW that goes high on access while in Rev B it is HIGH and goes LOW.

Thank you in advance Arye