Hey all,
This is hopefully a fairly straightforward question, but after reading the TRM for the F28075 the answer wasn't spelled out explicitly so I thought someone on here could verify.
I am looking to talk over SPI to a 16 bit external DAC that is looking for a 24 bit word to for each data point it puts out. I was planning to parse the data and configuration bits into 3 separate 8 bit chunks, and put them into 2 different FIFO word registers and the SPITXBUF register and let the SPI peripheral shift them out sequentially without delay. I know that the character length is set by the SPICHAR bit in the SPICCR register, I just want verification that if I set the SPICHAR length to 8 bits and that if I used the 3 word registers that I would get a 24 sequential bit stream. The documentation for the FIFO isn't very specific about this. I want to know if the hardware forces the FIFO register to shift out all 16 bits before moving on to the next FIFO register in the sequence.
Best regards,
Lance